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公开(公告)号：US07652465B2
公开(公告)日：2010-01-26
申请号：US11388428
申请日：2006-03-24
IPC分类号： G01R13/20
CPC分类号： G01R13/0254
摘要： A “no dead time” data acquisition system for a measurement instrument receives a digitized signal representing an electrical signal being monitored and generates from the digitized signal a trigger signal using a fast digital trigger circuit, the trigger signal including all trigger events within the digitized signal. The digitized signal is compressed as desired and delayed by a first-in, first-out (FIFO) buffer for a period of time to assure a predetermined amount of data prior to a first trigger event in the trigger signal. The delayed digitized signal is delivered to a fast rasterizer or drawing engine upon the occurrence of the first trigger event to generate a waveform image. The waveform image is then provided to a display buffer for combination with prior waveforms and/or other graphic inputs from other drawing engines. The contents of the display buffer are provided to a display at a display update rate to show a composite of all waveform images representing the electrical signal.
摘要翻译： 用于测量仪器的“无死区时间”数据采集系统接收表示正在监视的电信号的数字化信号，并且使用快速数字触发电路从数字化信号产生触发信号，触发信号包括数字化信号内的所有触发事件 。 数字化信号根据需要被压缩并且由先入先出（FIFO）缓冲器延迟一段时间，以确保在触发信号中的第一触发事件之前的预定量的数据。 延迟数字化信号在发生第一触发事件时被传送到快速光栅化器或绘图引擎以产生波形图像。 然后将波形图像提供给显示缓冲器，以与来自其它绘图引擎的先前波形和/或其他图形输入组合。 以显示更新率将显示缓冲器的内容提供给显示器，以显示表示电信号的所有波形图像的合成。
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公开(公告)号：US07352167B2
公开(公告)日：2008-04-01
申请号：US11388925
申请日：2006-03-24
IPC分类号： G01R13/20
CPC分类号： G01R13/0254
摘要： An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.
摘要翻译： 改进的数字触发电路具有从每个采样时钟周期的输入电信号提取的多个数据样本。 将多个数据样本并行地与高阈值电平和低阈值电平进行比较，其提供用于噪声抑制的滞后。 此外，多个数据样本用于确定子采样触发定位。 比较输出被输入到数字触发逻辑电路，用于识别所选择的触发事件并产生用于从输入电信号中采集数据的触发用于分析和显示。 数字触发逻辑提供边缘事件触发，脉冲宽度触发和转换时间触发等。
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公开(公告)号：US07558936B2
公开(公告)日：2009-07-07
申请号：US11388926
申请日：2006-03-24
IPC分类号： G06F12/00
CPC分类号： G06F5/14 , G01R13/029
摘要： A data management method for a long record length memory that is used for data acquisition writes data samples into an initial circular buffer within the memory having a size equal to a pre-trigger time. When a first trigger event occurs, the data samples are then written into a linear region after the circular buffer within the memory. The data sample acquisition in the linear region continues until a post-trigger and new pre-trigger time have elapsed after a last trigger event, at which point the acquisition terminates and the new pre-trigger time becomes a new circular buffer for a next trigger event. In this way all trigger events are captured with associated pre-trigger and post-trigger data.
摘要翻译： 用于数据采集的长记录长度存储器的数据管理方法将数据样本写入具有等于预触发时间的大小的存储器内的初始循环缓冲器。 当发生第一触发事件时，数据样本然后被写入存储器中的循环缓冲器之后的线性区域。 线性区域中的数据样本采集继续，直到最后一次触发事件发生后触发和新的预触发时间，此时采集终止，新的预触发时间成为新的循环缓冲区，用于下一个触发 事件。 以这种方式，所有触发事件都将被捕获与相关的预触发和后触发数据。
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公开(公告)号：US08374811B2
公开(公告)日：2013-02-12
申请号：US12631968
申请日：2009-12-07
申请人： Steven K. Sullivan , Kristie L. Veith , Terrance R. Beale , Paul M. Gerlach , Gregory A. Martin , George S. Walker
发明人： Steven K. Sullivan , Kristie L. Veith , Terrance R. Beale , Paul M. Gerlach , Gregory A. Martin , George S. Walker
CPC分类号： G01R13/0236 , G01R13/0254
摘要： A waveform display apparatus and method displays one or more waveforms of a signal under test at high throughput while acquiring digital data of the signal under test in a large acquisition memory. A user sets a time interval of user's interest when viewing a signal under test and sets trigger criteria through a user interface. An ADC converts the signal under test into digital data that is stored in a large acquisition memory. A trigger unit detects and produces trigger events, based on a trigger, as trigger event information during one acquisition process. A trigger event eliminator may discard some of the trigger events based on pre-trigger and post-conditions set through the interface by a user. The trigger events are recorded in a trigger list as the trigger event information. A control unit locates the digital data in the acquisition memory corresponding to the trigger events in the trigger list and displays a waveform associated with the trigger event for the time interval on a display device.
摘要翻译： 波形显示装置和方法以高吞吐量显示被测信号的一个或多个波形，同时在大的采集存储器中获取待测信号的数字数据。 用户在查看被测信号时设置用户兴趣的时间间隔，并通过用户界面设置触发条件。 ADC将被测信号转换为存储在大型采集存储器中的数字数据。 触发单元在一次采集过程中，根据触发信号检测并产生触发事件作为触发事件信息。 触发事件消除器可以基于用户通过接口设置的预触发和后置条件来丢弃一些触发事件。 触发事件记录在触发列表中作为触发事件信息。 控制单元将对应于触发列表中的触发事件的采集存储器中的数字数据定位在显示设备上，并且在时间间隔上显示与触发事件相关联的波形。
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公开(公告)号：US08059129B2
公开(公告)日：2011-11-15
申请号：US11393129
申请日：2006-03-29
IPC分类号： G06T1/60
CPC分类号： G09G5/39 , G01R13/02 , G09G2360/126
摘要： A fast rasterizer uses a fast memory that has a bit-set port for receiving data and a totally independent readout and clear port for outputting a waveform image. The fast memory is organized into rows and columns corresponding to the rows and columns of a raster display device, with each memory location or cell holding a single bit. The fast memory is divided into parallel sections so that one column of each section may be written into each clock cycle, resulting in the possibility of writing a plurality of columns into the fast memory each clock cycle. Each memory cell is set when a row and column write signal for the cell are asserted, and is read out and cleared when a row and column read signal for the cell are asserted. Row logic using thermometer codes is used to set the row lines for the selected column in each section.
摘要翻译： 快速光栅化器使用具有用于接收数据的位设置端口和用于输出波形图像的完全独立的读出和清除端口的快速存储器。 快速存储器被组织成与光栅显示设备的行和列相对应的行和列，每个存储器位置或单元保持单个位。 快速存储器被分为并行部分，使得每个部分的一列可以被写入每个时钟周期，导致在每个时钟周期将多个列写入快速存储器的可能性。 当单元的行和列写入信号被断言时，每个存储单元被置位，并且当单元的行和列读取信号被断言时被读出和清除。 使用温度计代码的行逻辑用于设置每个部分中所选列的行行。
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公开(公告)号：US07834780B2
公开(公告)日：2010-11-16
申请号：US11385170
申请日：2006-03-20
IPC分类号： H03M7/00
CPC分类号： G01R13/0272
摘要： A waveform compression and display technique saves both a peak detected version (background version) and a decimated/lowpass filtered version (foreground version) of a sampled electrical signal. The two versions are displayed simultaneously overlaid together in a contrasting manner so as not to obscure information contained in either of them. The lowpass filtered version uses a series of simple lowpass filters with decimation to produce a single data stream from a plurality of data streams derived from the sampled electrical signal. The single data stream may then be subjected to additional filtering, such as a cascaded integrator-comb filter, to obtain a desired frequency bandwidth. When displayed, the peak detect pixels adjacent the decimated/lowpass filtered pixels may be adjusted in intensity so that the low frequency information of the lowpass filtered waveform is not lost, while the peak detect pixels further from the lowpass filtered pixels are intensified to highlight the high frequency information. Alternatively the background version intensity may be controlled by a user control over a first range from zero to a predetermined maximum, and the foreground version may be controlled over a second range from a default intensity to a maximum, saturated intensity.
摘要翻译： 波形压缩和显示技术节省了采样电信号的峰值检测版本（背景版本）和抽取/低通滤波版本（前景版本）。 这两个版本以对比的方式同时叠加在一起，以免遮蔽其中任何一个中的信息。 低通滤波器版本使用一系列具有抽取的简单低通滤波器，以从采样的电信号导出的多个数据流产生单个数据流。 然后可以对单个数据流进行额外的滤波，例如级联的积分器梳状滤波器，以获得期望的频率带宽。 当显示时，与抽取/低通滤波的像素相邻的峰值检测像素的强度可以被调整，使得低通滤波波形的低频信息不会丢失，而从低通滤波像素进一步增加峰值，从而突出显示 高频信息。 或者，背景版本强度可以由用户在从零到预定最大值的范围内的控制来控制，并且可以在从默认强度到最大饱和强度的第二范围内控制前景版本。
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公开(公告)号：US07366628B2
公开(公告)日：2008-04-29
申请号：US11266105
申请日：2005-11-02
IPC分类号： G06F19/00
CPC分类号： H03M7/3066 , G01R31/31921
摘要： A test and measurement Instrument samples an input digital logic signal to produce logic samples, compresses the logic samples into compression codes, and stores the compression codes into acquisition memory. Compression includes parsing the logic samples into groups and assigning compression codes to those groups, and is performed so as not to lose information about the input digital logic signal's activity. The instrument converts the stored compression codes into a waveform image in display memory and displays the stored waveform image on a display device.
摘要翻译： 测试和测量仪器对输入数字逻辑信号进行采样以产生逻辑采样，将逻辑采样压缩为压缩代码，并将压缩代码存储到采集存储器中。 压缩包括将逻辑样本分解成组并将压缩码分配给这些组，并且被执行以便不丢失关于输入数字逻辑信号的活动的信息。 仪器将存储的压缩码转换为显示存储器中的波形图像，并将显示的存储的波形图像显示在显示设备上。
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8.发明授权Continually responsive and anticipating automatic setup function for a digital oscilloscope 失效持续响应并预测数字示波器的自动设置功能公开(公告)号：US06571185B1
公开(公告)日：2003-05-27
申请号：US09295070
申请日：1999-04-20
申请人： Michael A. Gauland , Steven K. Sullivan , Roy I. Siegel , Frederick A. Azinger , Charles L. Saxe
发明人： Michael A. Gauland , Steven K. Sullivan , Roy I. Siegel , Frederick A. Azinger , Charles L. Saxe
IPC分类号： G01R1302
CPC分类号： G01R13/02
摘要： Multiple views of the signal are generated by a time-sharing use of the oscilloscope's acquisition hardware. The instrument software makes a set of measurements of the input signal, and from the results of those measurements classifies the input signal as to type. Signals of particular types implicitly select suites of views of the signal. The operator sees examples of the other views available while a related view is the main view. Alternate views can be “live” miniature views, and displayed alongside in simplified form, alongside the main view. By clicking on them, these alternative views may be made to become the main view. The operator can add and modify views. Each view comes with a set of measurements that are automatically performed and the results are displayed on the screen as text annotation to the waveform. A different view of the signal comes with different automatic measurements, and presents the results of these measurements as annotations to the waveform image. These next alternative setups may be miniature “live” displays.
摘要翻译： 信号的多个视图通过示波器采集硬件的分时使用产生。 仪器软件对输入信号进行一组测量，并根据这些测量结果对输入信号进行分类。 特定类型的信号隐含地选择信号的视图的套件。 操作员可以看到可用的其他视图的示例，而相关视图是主视图。 另外的视图可以是“活的”微型视图，并且以简化的形式显示在主视图的旁边。 通过点击它们，可以将这些替代视图作为主视图。 操作员可以添加和修改视图。 每个视图都带有一组自动执行的测量结果，并将结果作为波形的文本注释显示在屏幕上。 信号的不同视图带有不同的自动测量，并将这些测量的结果呈现为波形图像的注释。 这些下一个替代设置可以是微型的“直播”显示器。
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公开(公告)号：US5521599A
公开(公告)日：1996-05-28
申请号：US323178
申请日：1994-10-14
CPC分类号： G11C27/026
摘要： A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an output of the second parallel delay element and which samples the strobe signal output of the second parallel delay element in response to an output of the third delay element, and further employs a control circuit which filters the difference between those two sampled output signals and provides that filtered difference as the control signal.
摘要翻译： 高速模拟信号采样系统。 该系统包括具有串联布置的多个延迟元件的定时链和具有响应于采样率倍增器中的第一，第二和第三并行延迟元件的输出的延迟锁定控制系统的采样率倍增器，以控制 第二并行延迟元件，使得其选通信号输出发生在第一并行延迟元件的选通信号输出与第三并行延迟元件之间的一半时间。 第一，第二和第三并行延迟元件是定时链的前三个并行延迟元件，并且延迟锁定控制系统的控制信号用于调整和控制由每个其它并行延迟元件引入的延迟量 第二并行延迟元件。 第二和第三并行延迟元件跨越定时链中的一个串联延迟元件，而第一并行延迟元件具有与第二并行延迟元件相同的输入。 延迟锁定控制系统采用采样电路，该采样电路响应于第二并行延迟元件的输出对第一并行延迟元件的选通信号输出进行采样，并且响应于输出对第二并行延迟元件的选通信号输出进行采样 并且进一步采用对这两个采样输出信号之间的差值进行滤波的控制电路，并提供该滤波差值作为控制信号。
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公开(公告)号：US5144525A
公开(公告)日：1992-09-01
申请号：US589222
申请日：1990-09-27
CPC分类号： G11C27/024 , G11C27/04
摘要： An analog acquisition system includes an array of analog capture cells for capturing and storing a signal on an analog bus. Each capture cell in the array may be sequentially selected for sampling the signal at successive sample times. Timing for selecting a row of the analog memory array is provided by a slow shift register and timing for selecting a capture cell within the row of the analog memory array is provided by a fast tapped delay line. Additional circuitry is provided for controlling the delay of the tapped delay line such that total delay is equal to the time the slow shift register takes to transfer from one row to the next.
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