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公开(公告)号：US5521599A
公开(公告)日：1996-05-28
申请号：US323178
申请日：1994-10-14
CPC分类号： G11C27/026
摘要： A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an output of the second parallel delay element and which samples the strobe signal output of the second parallel delay element in response to an output of the third delay element, and further employs a control circuit which filters the difference between those two sampled output signals and provides that filtered difference as the control signal.
摘要翻译： 高速模拟信号采样系统。 该系统包括具有串联布置的多个延迟元件的定时链和具有响应于采样率倍增器中的第一，第二和第三并行延迟元件的输出的延迟锁定控制系统的采样率倍增器，以控制 第二并行延迟元件，使得其选通信号输出发生在第一并行延迟元件的选通信号输出与第三并行延迟元件之间的一半时间。 第一，第二和第三并行延迟元件是定时链的前三个并行延迟元件，并且延迟锁定控制系统的控制信号用于调整和控制由每个其它并行延迟元件引入的延迟量 第二并行延迟元件。 第二和第三并行延迟元件跨越定时链中的一个串联延迟元件，而第一并行延迟元件具有与第二并行延迟元件相同的输入。 延迟锁定控制系统采用采样电路，该采样电路响应于第二并行延迟元件的输出对第一并行延迟元件的选通信号输出进行采样，并且响应于输出对第二并行延迟元件的选通信号输出进行采样 并且进一步采用对这两个采样输出信号之间的差值进行滤波的控制电路，并提供该滤波差值作为控制信号。
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2.发明授权公开(公告)号：US07068788B2
公开(公告)日：2006-06-27
申请号：US09949560
申请日：2001-09-10
CPC分类号： H04K1/02
摘要： The present invention is related to digital to analog converter (DAC) input data encryption off-chip and decryption on-chip to suppress input data in-band harmonic leakage through package related parasitic capacitance. More specifically, the present invention relates to the method and apparatus of input data encryption off-chip by forming the logical exclusive-OR of the raw data and a random single bit data stream. The encrypted data is then read onto the DAC chip where the data is decrypted using identical circuitry and an identical random single bit data stream. The off-chip encryption isolates harmonic content within the input data, preventing leakage of input data harmonic content through IC package-related parasitic capacitance into DAC outputs. Any leakage appears as an increase in spectral noise rather than output distortion and as such, has a much smaller impact on DAC narrow band linearity.
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公开(公告)号：US06359467B1
公开(公告)日：2002-03-19
申请号：US09684564
申请日：2000-10-05
IPC分类号： G06F738
CPC分类号： G06F7/762 , H03M1/0673 , H03M1/74
摘要： The present invention is a technique for dynamic element matching used in digital-to-analog converters (DAC's). An analog-to-digital converter (ADC) converts an analog signal into a digital code. A current-mode randomizer randomizes the digital code based on a control word provided by a pseudo random number generator. A digital-to-analog converter (DAC) converts the randomized digital code into an analog signal.
摘要翻译： 本发明是用于数模转换器（DAC）中的动态元件匹配技术。 模拟 - 数字转换器（ADC）将模拟信号转换为数字码。 电流模式随机化器根据由伪随机数发生器提供的控制字随机化数字码。 数模转换器（DAC）将随机数字码转换为模拟信号。
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公开(公告)号：US5781036A
公开(公告)日：1998-07-14
申请号：US834713
申请日：1997-04-01
CPC分类号： H03L7/0896 , H03D13/00
摘要： A phase detector biased in a manner to alleviate the mismatch between the biasing current sources and the phase detector core bias currents. The bias setting resistors are coupled together at a common node that forms the negative input of a differential feedback amplifier. The positive input to the amplifier is referenced to a reference voltage, and the output of the amplifier controls the biasing current sources. The feedback amplifier forces the average voltage at the current source outputs to approximately match the reference voltage applied to its positive input. Thus the average bias current from the bias current sources is forced to track the average bias currents of the phase detector core.
摘要翻译： 相位检测器被偏置以减轻偏置电流源与相位检测器芯偏置电流之间的失配。 偏置设置电阻在形成差分反馈放大器的负输入的公共节点处耦合在一起。 放大器的正输入参考参考电压，放大器的输出控制偏置电流源。 反馈放大器迫使电流源输出端的平均电压与施加到其正输入端的参考电压近似匹配。 因此，来自偏置电流源的平均偏置电流被迫跟踪相位检测器芯的平均偏置电流。
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公开(公告)号：US06211806B1
公开(公告)日：2001-04-03
申请号：US09392069
申请日：1999-09-08
IPC分类号： H03M138
CPC分类号： H03M1/0695 , H03M1/0624 , H03M1/168
摘要： The present invention discloses a method and apparatus for correcting errors in N digital word generated by N+1 pipelined analog-to-digital converters. The method comprises the steps of: (1) synchronizing the N digital words by N groups of pipeline registers; and (2) correcting the synchronized N digital words by performing either an incrementing operation or a decrementing operation based on an adjustment value.
摘要翻译： 本发明公开了一种用于校正由N + 1流水线模数转换器产生的N个数字字中的错误的方法和装置。 该方法包括以下步骤：（1）通过N组流水线寄存器同步N个数字字; 和（2）通过执行基于调整值的递增运算或递减运算来校正同步的N个数字字。
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6.发明授权Digital calibration for analog-to-digital converters with implicit gain proration 失效具有隐含增益分配的模数转换器的数字校准
公开(公告)号：US5977894A
公开(公告)日：1999-11-02
申请号：US1340
申请日：1997-12-31
CPC分类号： H03M1/1061 , H03M1/167
摘要： A method of digital calibration for analog-to-digital converters providing implicit gain proration. In accordance with the method, the calibration begins at the center of the transfer curve rather from one end or the other. By beginning in the center, calibrating in the positive direction and then calibrating in the negative direction, the interstage gain errors are also corrected without an extra gain-proration cycle. In addition, the number of accumulated measurements is reduced by a factor of two for the final correction coefficient by using the preferred method. Therefore, the roundoff errors are also reduced.
摘要翻译： 提供隐式增益分配的模数转换器的数字校准方法。 根据该方法，校准开始于传输曲线的中心，而不是从一端或另一端开始。 从中心开始，在正方向校准，然后在负方向校准，也可以在没有额外的增益 - 循环周期的情况下校正级间增益误差。 此外，通过使用优选方法，对于最终校正系数，累积测量的数量减少了2倍。 因此，舍入误差也减少。
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7.发明授权
公开(公告)号：US5672961A
公开(公告)日：1997-09-30
申请号：US581131
申请日：1995-12-29
摘要： A current source includes a control stage responsive to a stable, d.c. input voltage that is operative to produce a control voltage proportional to absolute temperature (PTAT), and an output stage responsive to the PTAT control voltage that is operative to produce an output current that is an essentially constant fraction of an output constant current source. The control stage includes a temperature-dependent control resistor of a given resistor type, and at least one control constant current source providing the control resistor with a temperature dependent control current. The temperature dependent current source includes a temperature dependent current source resistor based on the given resistor type such that the temperature dependencies of the control current and the control resistor tend to cancel in such a manner that a true PTAT control voltage is developed. The output stage includes an output transistor coupled to an output constant current source such that an output current of the output stage has no current contribution other than from the output current source. A method for providing a current that is a constant fraction of an output constant current source includes the steps of: (a) developing a control current that is based on the same resistor type as a control resistor; (b) applying the control current to the control resistor to develop a control voltage that is proportional to absolute temperature; and (c) applying the control voltage to a current divider coupled to an output constant source to provide an output current.
摘要翻译： 电流源包括响应于稳定的直流电的控制级。 可操作地产生与绝对温度（PTAT）成比例的控制电压的输入电压，以及响应于PTAT控制电压的输出级，该输出级用于产生输出电流源，输出电流基本上是恒定分量的输出恒定电流源。 控制级包括给定电阻器类型的温度依赖性控制电阻器和至少一个控制恒流源，为控制电阻器提供温度依赖控制电流。 温度相关电流源包括基于给定电阻器类型的温度依赖电流源电阻器，使得控制电流和控制电阻器的温度依赖性倾向于消除真正的PTAT控制电压的方式。 输出级包括耦合到输出恒定电流源的输出晶体管，使得输出级的输出电流除了来自输出电流源之外没有电流贡献。 提供作为输出恒流源的恒定分量的电流的方法包括以下步骤：（a）开发基于与控制电阻器相同的电阻器类型的控制电流; （b）将控制电流施加到控制电阻器以产生与绝对温度成比例的控制电压; 和（c）将控制电压施加到耦合到输出恒定源的分流器以提供输出电流。
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公开(公告)号：US5331210A
公开(公告)日：1994-07-19
申请号：US32032
申请日：1993-03-16
IPC分类号： G01R19/04 , G11C27/00 , H03K5/1532 , H03K5/24
CPC分类号： H03K5/1532 , G01R19/04
摘要： A fully differential CMOS peak detection circuit has a differential input stage and a negative feedback loop that form a differential unity gain feedback amplifier. The differential output of the differential input stage is applied to a differential peak detect circuit having a pair of series diode/capacitor combinations. The diode/capacitor junctions are applied to differential inputs of the negative feedback loop. A common mode correction circuit is coupled to the differential CMOS peak detection circuit to minimize differences between the common mode voltages of the differential input stage and the negative feedback loop. The differential peak voltage is held at the differential output of the differential input stage for sampling by a sampling circuit during a readback interval, and then tracks a differential input signal applied to the differential input of the differential input stage during a tracking interval. The differential peak detection circuit then peak detects during a peak detect interval that is equal to a desired sample time window.
摘要翻译： 全差分CMOS峰值检测电路具有形成差分单位增益反馈放大器的差分输入级和负反馈环路。 差分输入级的差分输出被施加到具有一对串联二极管/电容器组合的差分峰值检测电路。 二极管/电容器结连接到负反馈回路的差分输入端。 共模校正电路耦合到差分CMOS峰值检测电路，以最小化差分输入级的共模电压和负反馈回路之间的差异。 差分峰值电压保持在差分输入级的差分输出端，用于在回读间隔期间由采样电路进行采样，然后跟踪在跟踪间隔期间施加到差分输入级的差分输入的差分输入信号。 然后峰值检测电路在峰值检测间隔期间检测到等于所需采样时间窗口。
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