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    Iimplementing enhanced aperture function calibration for logic built in self test (LBIST)
    3.
    发明授权
    Iimplementing enhanced aperture function calibration for logic built in self test (LBIST) 有权
    实现内置自检逻辑（LBIST）逻辑的增强孔径功能校准

    公开(公告)号：US08627162B2

    公开(公告)日：2014-01-07

    申请号：US13316620

    申请日：2011-12-12

    申请人： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    发明人： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318385 ,  G01R31/318547 ,  G01R31/3187

    摘要： A method and circuits for implementing aperture function calibration for Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. The aperture function calibration uses aperture calibration data, and an LBIST calibration channel having a predefined number of scan inversions between the aperture calibration data and a multiple input signature register (MISR). LBIST is run selecting the LBIST calibration channel and masking other LBIST channels to the MISR. A change in the MISR value, for example, from zero to a non-zero value, is identified and an aperture adjustment is calculated and used to identify any needed adjustment of aperture edges.

    摘要翻译： 用于实现逻辑内置自检（LBIST）诊断的孔径函数校准的方法和电路，以及提供主题电路所在的设计结构。 孔径功能校准使用孔径校准数据，以及LBIST校准通道，其具有孔径校准数据和多输入特征寄存器（MISR）之间的预定数量的扫描反转。 LBIST运行选择LBIST校准通道，并将其他LBIST通道屏蔽到MISR。 识别MISR值的变化，例如从零到非零值，并且计算孔径调整并用于识别孔径边缘的任何所需的调整。

    IMPLEMENTING ENHANCED PSEUDO RANDOM PATTERN GENERATORS WITH HIERARCHICAL LINEAR FEEDBACK SHIFT REGISTERS (LFSRs)
    4.
    发明申请
    IMPLEMENTING ENHANCED PSEUDO RANDOM PATTERN GENERATORS WITH HIERARCHICAL LINEAR FEEDBACK SHIFT REGISTERS (LFSRs) 有权
    实现具有分层线性反馈移位寄存器（LFSR）的增强型PSEUDO随机模式发生器

    公开(公告)号：US20130191695A1

    公开(公告)日：2013-07-25

    申请号：US13353727

    申请日：2012-01-19

    申请人： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    发明人： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC分类号： G06F11/27

    CPC分类号： G06F11/27 ,  G01R31/318385

    摘要： A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.

    摘要翻译： 一种用于实现增强型逻辑内置自检（LBIST）诊断的方法和电路，以及提供主题电路所在的设计结构。 提供了多个伪随机模式发生器（PRPG），每个PRPG包括一个或多个线性反馈移位寄存器（LFSR）。 每个相应的PRPG包括选择性地接收来自另一PRPG的反馈和相应PRPG的预定义输入的异或反馈输入。 相应的XOR扩展功能被耦合到每个PRPG的多个输出，其中预定义的XOR扩展函数将测试伪随机模式输入应用于LBIST通道用于LBIST诊断。

    Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression
    5.
    发明授权
    Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression 失效
    通过信道抑制在逻辑内置自检（LBIST）中降低功耗

    公开(公告)号：US07793184B2

    公开(公告)日：2010-09-07

    申请号：US11622048

    申请日：2007-01-11

    申请人： Steven M. Douskey

    发明人： Steven M. Douskey

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31721 ,  G01R31/318544 ,  G01R31/318575 ,  G01R31/3187

    摘要： A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a plurality of LBIST channels do not contribute to a particular test and excluding from that particular test each LBIST channel that does not contribute to that particular test.

    摘要翻译： 介绍了片上测试的方法，系统和计算机可读介质。 在一个实施例中，所述方法，系统或计算机可读介质包括识别多个LBIST信道中的哪些LBIST信道对特定测试没有贡献，并从该特定测试中排除对该特定测试无贡献的每个LBIST信道。

    TESTING AND OPERATING A MULTIPROCESSOR CHIP WITH PROCESSOR REDUNDANCY
    6.
    发明申请
    TESTING AND OPERATING A MULTIPROCESSOR CHIP WITH PROCESSOR REDUNDANCY 有权
    测试和操作具有处理器冗余的多处理器芯片

    公开(公告)号：US20130031418A1

    公开(公告)日：2013-01-31

    申请号：US13196459

    申请日：2011-08-02

    申请人： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

    发明人： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

    IPC分类号： G06F11/28

    CPC分类号： G06F11/2242 ,  G06F11/202

    摘要： A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

    摘要翻译： 一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。 第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。 第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。 如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。 响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。 片上逻辑根据所选的物理到逻辑映射配置处理器内核。

    SELF-TEST DESIGN METHODOLOGY AND TECHNIQUE FOR ROOT-GATED CLOCKING STRUCTURE
    7.
    发明申请
    SELF-TEST DESIGN METHODOLOGY AND TECHNIQUE FOR ROOT-GATED CLOCKING STRUCTURE 有权
    自闭式钟表结构的自我测试设计方法与技术

    公开(公告)号：US20100231281A1

    公开(公告)日：2010-09-16

    申请号：US12401730

    申请日：2009-03-11

    申请人： Steven M. Douskey ,  Ryan A. Fitch ,  Brandon E. Schenck

    发明人： Steven M. Douskey ,  Ryan A. Fitch ,  Brandon E. Schenck

    IPC分类号： H03K3/00

    CPC分类号： G01R31/31727 ,  G06F1/04 ,  G06F1/10

    摘要： In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

    摘要翻译： 在产生用于电平敏感扫描设计锁存器的时钟信号的方法中，至少一个测试输入信号被发送到多个分离器叶片。 一旦测试输入信号稳定在每个分路器叶片，则产生具有来自中央根部的预定脉冲模式的整形振荡器时钟信号。 在多个分路器叶片处，测试输入信号与整形振荡器时钟信号逻辑组合，从而产生第一锁存时钟信号和第二锁存时钟信号。 逻辑组合动作包括将小于一个时钟周期的延迟施加到整形振荡器时钟信号以产生延迟的振荡器时钟信号; 将延迟的振荡器时钟信号与第二信号逻辑地组合，以便产生第一锁存时钟信号; 并且将所述整形振荡器时钟信号与第三信号逻辑地组合，以便产生所述第二锁存时钟信号。

    Dynamic scan
    9.
    发明授权
    Dynamic scan 失效
    动态扫描

    公开(公告)号：US08516318B2

    公开(公告)日：2013-08-20

    申请号：US12968627

    申请日：2010-12-15

    申请人： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    发明人： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC分类号： G06F11/00

    CPC分类号： G01R31/318558

    摘要： In a test data access system, a shift register is coupled the test data in pin. A first multiplexer is in data communication with the TDI pin and is configured to receive data from the TDI pin and to transmit data to each of the instruments. The first multiplexer is also configured to receive data from a data recirculation bit and to transmit data from the TDI pin to a plurality of instruments when the recirculation bit has a first value and to transmit data to the plurality of instruments from a recirculation line when the recirculation bit has a second value, different from the first value. A second multiplexer is configured to receive data from each of the plurality of instruments and is configured to transmit data from a selected one of the plurality of instruments, selected based on a value of data in the shift register. A first AND gate is configured to generate a gates clock to the shift register. A second AND gate is responsive to the first AND gate, configured to lock the shift register. A third AND gate, responsive to the first AND gate, is configured to control clocking to the plurality of instruments.

    摘要翻译： 在测试数据访问系统中，移位寄存器以引脚方式耦合测试数据。 第一个多路复用器与TDI引脚进行数据通信，并配置为从TDI引脚接收数据并向每个仪器传输数据。 第一多路复用器还被配置为从数据再循环位接收数据，并且当再循环位具有第一值时将数据从TDI引脚传输到多个仪器，并且当第二复用器当再循环线时将数据从再循环管线传送到多个仪器 再循环位具有与第一值不同的第二值。 第二多路复用器被配置为从所述多个仪器中的每一个接收数据，并且被配置为基于所述移位寄存器中的数据值来选择所选择的所述多个仪器中的数据。 第一与门被配置为向移位寄存器产生门时钟。 第二与门响应于第一与门，被配置为锁定移位寄存器。 响应于第一与门的第三与门配置成控制对多个仪器的时钟。

    Dynamic Scan
    10.
    发明申请
    Dynamic Scan 失效
    动态扫描

    公开(公告)号：US20120159273A1

    公开(公告)日：2012-06-21

    申请号：US12968627

    申请日：2010-12-15

    申请人： Steven M. Douskey ,  Ryan Andrew Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    发明人： Steven M. Douskey ,  Ryan Andrew Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/318558

    摘要： In a test data access system, a shift register is coupled the test data in pin. A first multiplexer is in data communication with the TDI pin and is configured to receive data from the TDI pin and to transmit data to each of the instruments. The first multiplexer is also configured to receive data from a data recirculation bit and to transmit data from the TDI pin to a plurality of instruments when the recirculation bit has a first value and to transmit data to the plurality of instruments from a recirculation line when the recirculation bit has a second value, different from the first value. A second multiplexer is configured to receive data from each of the plurality of instruments and is configured to transmit data from a selected one of the plurality of instruments, selected based on a value of data in the shift register. A first AND gate is configured to generate a gates clock to the shift register. A second AND gate is responsive to the first AND gate, configured to lock the shift register. A third AND gate, responsive to the first AND gate, is configured to control clocking to the plurality of instruments.

    摘要翻译： 在测试数据访问系统中，移位寄存器以引脚方式耦合测试数据。 第一个多路复用器与TDI引脚进行数据通信，并配置为从TDI引脚接收数据并向每个仪器传输数据。 第一多路复用器还被配置为从数据再循环位接收数据，并且当再循环位具有第一值时将数据从TDI引脚传输到多个仪器，并且当第二复用器当再循环线时将数据从再循环管线传送到多个仪器 再循环位具有与第一值不同的第二值。 第二多路复用器被配置为从所述多个仪器中的每一个接收数据，并且被配置为基于所述移位寄存器中的数据值来选择所选择的所述多个仪器中的数据。 第一与门被配置为向移位寄存器产生门时钟。 第二与门响应于第一与门，被配置为锁定移位寄存器。 响应于第一与门的第三与门配置成控制对多个仪器的时钟。