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93 条记录 (耗时 0.03 秒)

    Bias circuit for a MOS device
    1.
    发明授权
    Bias circuit for a MOS device 有权
    用于MOS器件的偏置电路

    公开(公告)号：US07936208B2

    公开(公告)日：2011-05-03

    申请号：US12184148

    申请日：2008-07-31

    申请人： Steven Mark Clements ,  Hayden C. Cranford, Jr. ,  Amar Chandra Mahadeo Dwarka ,  John Farley Ewen

    发明人： Steven Mark Clements ,  Hayden C. Cranford, Jr. ,  Amar Chandra Mahadeo Dwarka ,  John Farley Ewen

    IPC分类号： G05F3/02

    CPC分类号： G05F3/205

    摘要： A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

    摘要翻译： 公开了一种用于向MOS器件提供偏置电压的方法和电路。 该方法和电路包括利用至少一个二极管连接的电路来提供跟踪半导体器件的工艺，电压和温度变化的电压。 所述方法和电路包括利用耦合到所述至少一个二极管连接的电路的电流镜电路，以从所述电压产生所述半导体器件的主体的偏置电压。 偏置电压允许对过程，电压和温度变化进行补偿。

    One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery
    2.
    发明授权
    One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
    单采样每位决策反馈均衡器（DFE）时钟和数据恢复

    公开(公告)号：US07809054B2

    公开(公告)日：2010-10-05

    申请号：US11405997

    申请日：2006-04-18

    申请人： Juan A. Carballo ,  Hayden C. Cranford, Jr. ,  Gareth J. Nicholls ,  Vernon R. Norman ,  Martin L. Schmatz

    发明人： Juan A. Carballo ,  Hayden C. Cranford, Jr. ,  Gareth J. Nicholls ,  Vernon R. Norman ,  Martin L. Schmatz

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03063

    摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

    摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

    Method for on-chip diagnostic testing and checking of receiver margins
    4.
    发明授权
    Method for on-chip diagnostic testing and checking of receiver margins 失效
    用于片上诊断测试和接收器边距检查的方法

    公开(公告)号：US07721134B2

    公开(公告)日：2010-05-18

    申请号：US11566576

    申请日：2006-12-04

    申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

    发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

    IPC分类号： H04L25/00 ,  H03D3/24

    CPC分类号： G01R31/3171 ,  B82Y25/00 ,  G01R33/093

    摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.

    摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。

    Generating an eye diagram of integrated circuit transmitted signals
    5.
    发明授权
    Generating an eye diagram of integrated circuit transmitted signals 失效
    生成集成电路传输信号的眼图

    公开(公告)号：US07684478B2

    公开(公告)日：2010-03-23

    申请号：US11427831

    申请日：2006-06-30

    申请人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    发明人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    IPC分类号： H04B17/00 ,  H04L27/06

    CPC分类号： G01R31/31711 ,  H04L1/205 ,  H04L1/24

    摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.

    摘要翻译： 通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计 采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。

    Using statistical signatures for testing high-speed circuits
    6.
    发明授权
    Using statistical signatures for testing high-speed circuits 失效
    使用统计特征来测试高速电路

    公开(公告)号：US07661052B2

    公开(公告)日：2010-02-09

    申请号：US12021950

    申请日：2008-01-29

    申请人： Hayden C. Cranford, Jr. ,  Vernon R. Norman ,  Martin L. Schmatz

    发明人： Hayden C. Cranford, Jr. ,  Vernon R. Norman ,  Martin L. Schmatz

    IPC分类号： G06F11/277 ,  G06F11/16

    CPC分类号： G01R31/31901 ,  G01R31/31707

    摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.

    摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。

    Precision passive circuit structure
    7.
    发明授权
    Precision passive circuit structure 失效
    精密无源电路结构

    公开(公告)号：US07566946B2

    公开(公告)日：2009-07-28

    申请号：US11865432

    申请日：2007-10-01

    申请人： Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

    发明人： Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

    IPC分类号： H01C10/00

    CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

    摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

    Design structure for a serial link output stage differential amplifier
    8.
    发明授权
    Design structure for a serial link output stage differential amplifier 失效
    串行输出级差分放大器的设计结构

    公开(公告)号：US07522000B2

    公开(公告)日：2009-04-21

    申请号：US12114984

    申请日：2008-05-05

    申请人： Carrie E. Cox ,  Hayden C. Cranford, Jr.

    发明人： Carrie E. Cox ,  Hayden C. Cranford, Jr.

    IPC分类号： H03F3/45

    CPC分类号： H03F1/523 ,  H03F1/52 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2203/45244 ,  H03F2203/45342 ,  H03F2203/45456 ,  H03F2203/45466 ,  H03F2203/45702

    摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.

    摘要翻译： 一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试设计，用于传输由具有有限的最大电压容限的薄氧化物晶体管形成的差分放大器所需的较高幅度输出，这些最小电压容限符合通信协议 标准要求处理电压，在转换期间，可以通过在断电条件下限制任何两个器件端子上的电压来提供所需的电平。

    Body-biased enhanced precision current mirror
    10.
    发明授权
    Body-biased enhanced precision current mirror 失效
    车身偏置增强型精密电流镜

    公开(公告)号：US07501880B2

    公开(公告)日：2009-03-10

    申请号：US10906628

    申请日：2005-02-28

    申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr.

    发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr.

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262

    摘要： A body-biased enhanced current mirror circuit is disclosed wherein the body voltage of a current mirror device is adjusted to compensate for the effect of changes in the output voltage on the output current, increasing the output impedance. For each instance of the current mirror, this approach has the advantage of requiring no additional margin in operating voltage and of consuming no more circuit area than prior art current mirror designs. In addition, the body-biased enhanced current mirror circuit provides a stable reference current to output current ratio over a wide operating range. An auxiliary MOSFET current mirror device with the body connected to ground may be added in parallel with the body-biased current mirror device to eliminate a non-monotonicity of the current output.

    摘要翻译： 公开了体偏置增强电流镜电路，其中调整电流镜装置的体电压以补偿输出电压对输出电流的变化的影响，增加输出阻抗。 对于电流镜的每个实例，这种方法的优点在于不需要额外的工作电压余量，并且消耗的电路面积比现有技术的电流镜设计更多。 此外，体偏置增强电流镜电路在宽的工作范围内提供稳定的参考电流至输出电流比。 可以将主体连接到地的辅助MOSFET电流镜装置与主体偏置电流镜装置并联，以消除电流输出的非单调性。