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1.发明授权Nodal charge compensation for SST driver having data mux in output stage 失效具有输出级数据复用器的SST驱动器的节点充电补偿公开(公告)号：US07511530B1
公开(公告)日：2009-03-31
申请号：US12179957
申请日：2008-07-25
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H03K19/018507 , H03K17/693 , H04L25/0272
摘要： An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operation to discharge a node in the SST output stage for the purpose of removing the stored charge before the next transition cycle of the output stage.
摘要翻译： 具有用于最小化SST驱动器中的数据相关抖动并且增加SST驱动器中的频率振幅的附加电路的（SST）驱动器电路。 附加电路包括多个开关，其被配置为在操作期间暂时导通或脉冲以对SST输出级中的节点放电，以便在输出级的下一个转换周期之前去除存储的电荷。
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公开(公告)号：US07522000B2
公开(公告)日：2009-04-21
申请号：US12114984
申请日：2008-05-05
IPC分类号： H03F3/45
CPC分类号： H03F1/523 , H03F1/52 , H03F3/45183 , H03F3/45632 , H03F2203/45244 , H03F2203/45342 , H03F2203/45456 , H03F2203/45466 , H03F2203/45702
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.
摘要翻译： 一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试设计，用于传输由具有有限的最大电压容限的薄氧化物晶体管形成的差分放大器所需的较高幅度输出，这些最小电压容限符合通信协议 标准要求处理电压，在转换期间，可以通过在断电条件下限制任何两个器件端子上的电压来提供所需的电平。
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公开(公告)号：US07411422B2
公开(公告)日：2008-08-12
申请号：US11103789
申请日：2005-04-12
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/03885 , H04L25/0272 , H04L25/03343
摘要： A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.
摘要翻译： 高速串行数据通信系统包括用于校正均衡误差的规定，特别是由均衡器非理想性引入的错误。 在数据发射机上实现均衡，并且基于差分对的输出处的动态电流减法。 当位时间> 0时，误差电流从总驱动器电流中去除或减去，从而保持从位时间0到位时间> 0的恒定总电流。 通过使用相反性别的场效应晶体管减去位时间> 0时的电流，也可以实现相同的结果。 误差电流可以从仿真或使用驱动程序的副本通过反馈凭经验确定。 用于实现均衡纠错的电路和所得到的电网分析被显示和描述。
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4.发明授权High speed serial link output stage having self adaptation for various impairments 失效具有各种损伤的自适应的高速串行链路输出级公开(公告)号：US07769057B2
公开(公告)日：2010-08-03
申请号：US12175846
申请日：2008-07-18
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译： 提供了一种高速串行链路结构和方法，包括数据驱动器和复制驱动器结构，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。
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5.发明授权公开(公告)号：US07570071B2
公开(公告)日：2009-08-04
申请号：US12028451
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28 , G01R35/00 , H03K19/003 , G06F19/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
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公开(公告)号：US07391266B2
公开(公告)日：2008-06-24
申请号：US11531714
申请日：2006-09-14
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/52 , H03F1/523 , H03F3/45632 , H03F2203/45244 , H03F2203/45342 , H03F2203/45456 , H03F2203/45466 , H03F2203/45702
摘要： Protection for the transmission of higher amplitude outputs required of differential amplifiers formed by thin oxide transistors with limited maximum voltage tolerance used where compliance with communication protocol standards requires handling voltages which may, in transition, exceed desirable levels is provided by limiting the voltage across any two device terminals under power down conditions.
摘要翻译： 用于传输由具有有限的最大电压容限的薄氧化物晶体管形成的差分放大器所需的较高幅度输出所需的保护，这些限制在符合通信协议标准要求处理可能在转换中超过所需电平的电压时通过限制任何两个电压 设备端子处于掉电状态。
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公开(公告)号：US07698802B2
公开(公告)日：2010-04-20
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.
摘要翻译： 一种用于制造芯片上的有源电路的校准装置的方法，包括：提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。 所述校准机构产生控制输出，并且包括被配置为所述有源电路的至少一个段的复制品的被测器件（DUT），并且基于所述被测器件的比较，产生对所述控制输出进行有限调整的测试输出 具有已知电特性的DUT所呈现的电特性。 该方法还包括：将有源电路的每个控制输入端连接到校准机构的相应控制输出。 校准机构的控制输出动态调整施加到有源电路的器件的控制输入，以迫使有源电路呈现所需的电特性。
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8.发明授权Receiver termination circuit for a high speed direct current (DC) serial link 有权用于高速直流（DC）串行链路的接收器终端电路公开(公告)号：US07995660B2
公开(公告)日：2011-08-09
申请号：US11930975
申请日：2007-10-31
CPC分类号： H04L25/0294 , H04L25/0276
摘要： A method for matching receiver and transmitter common-mode voltages for a high-speed direct current (DC) serial connection between the receiver and the transmitter includes measuring, at the receiver, a common-mode voltage of the transmitter. The common-mode voltage of the transmitter is an average of a voltage signal transmitted by the transmitter and received by the receiver. The method further includes comparing the common-mode voltage of the transmitter with a common-mode voltage of the receiver. The method further includes maintaining the common-mode voltage of the receiver at a first level at which the common-mode voltage of the receiver substantially matches the common-mode voltage of the transmitter.
摘要翻译： 用于匹配接收机和发射机之间的高速直流（DC）串行连接的接收机和发射机共模电压的方法包括在接收机处测量发射机的共模电压。 发射机的共模电压是发射机发射并由接收机接收的电压信号的平均值。 该方法还包括将发射器的共模电压与接收器的共模电压进行比较。 该方法还包括将接收器的共模电压维持在接收器的共模电压基本上与发射机的共模电压相匹配的第一电平。
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9.发明授权Method for performing high speed serial link output stage having self adaptation for various impairments 失效用于执行具有针对各种损伤的自适应的高速串行链路输出级的方法公开(公告)号：US07460602B2
公开(公告)日：2008-12-02
申请号：US11119505
申请日：2005-04-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0292 , H04L25/03885
摘要： A high speed serial link method is provided, using a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
摘要翻译： 提供了使用数据驱动器和复制驱动器结构的高速串行链路方法，复制驱动器结构包括复制驱动器，校准引擎和峰值电平检测器。 校准引擎将峰值电平检测器输出与参考值进行比较，并响应于执行数据驱动器调整，其中数据驱动器调整包括驱动器偏置调整，驱动器中间级带宽调整和驱动器均衡设置调整中的至少一个。 在一些实施例中，校准引擎包括比较器和数字状态机; 在其他实施例中，它包括模拟运算放大器。
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10.发明授权公开(公告)号：US07368902B2
公开(公告)日：2008-05-06
申请号：US11262101
申请日：2005-10-28
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R35/00 , H03K19/003 , G06F19/00
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
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