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    Method for defining and using a timing model for an electronic circuit
    4.
    发明授权
    Method for defining and using a timing model for an electronic circuit 失效
    用于定义和使用电子电路定时模型的方法

    公开(公告)号：US5452225A

    公开(公告)日：1995-09-19

    申请号：US185641

    申请日：1994-01-24

    申请人： Mark E. Hammer

    发明人： Mark E. Hammer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A computer implemented method that first simulates the electronic circuit of each cell type within a circuit cell library using combinations of input transition time and load capacitances. The method reduces the results of the simulation to one of several models for the cell type. The method then reads an actual circuit description of the electronic circuit, and applies the models to the actual cells used in the circuit to determine signal delay through the circuit.

    摘要翻译： 一种计算机实现的方法，其首先使用输入转换时间和负载电容的组合来模拟电路单元库内的每个单元类型的电子电路。 该方法将模拟的结果减少到单元格类型的几个模型之一。 然后，该方法读取电子电路的实际电路描述，并将模型应用于电路中使用的实际单元，以确定通过电路的信号延迟。

    Method of extracting parasitic capacitance values from the physical design of an integrated circuit
    5.
    发明授权
    Method of extracting parasitic capacitance values from the physical design of an integrated circuit 失效
    从集成电路的物理设计中提取寄生电容值的方法

    公开(公告)号：US5706206A

    公开(公告)日：1998-01-06

    申请号：US566248

    申请日：1995-12-01

    申请人： Mark E. Hammer ,  Philip J. Johnson

    发明人： Mark E. Hammer ,  Philip J. Johnson

    IPC分类号： H01L21/82 ,  G01R27/26 ,  G06F17/50

    CPC分类号： G06F17/5081 ,  G01R27/2605

    摘要： A method of extracting parasitic capacitance values from the physical design of an integrated circuit, and more particularly, to a method of extracting lateral coupling and fringing capacitance values from the physical design of an integrated circuit, wherein the integrated circuit comprises multiple layers of conductors, each conductor having one or more lateral edges. The method comprises the steps of identifying each conductor's one or more lateral edges; fragmenting the lateral edges of each conductor into edge fragments based on a number of conductors present in layers above and/or below a given lateral edge; identifying the edge fragments which are laterally adjacent to each edge fragment; computing one or more relationships between an edge fragment and each of its laterally adjacent edge fragments; retrieving parasitic capacitance data for each edge fragment; and using the retrieved parasitic capacitance data to compute one or more parasitic capacitance values for each edge fragment. Disadvantages of prior methods are overcome in that extracted lateral coupling capacitances are based on the presence of conductors running above and/or below a given lateral conductor edge, and fringing capacitances are based on the spacing between a given lateral conductor edge and a laterally adjacent conductor edge.

    摘要翻译： 一种从集成电路的物理设计中提取寄生电容值的方法，更具体地说，涉及从集成电路的物理设计中提取横向耦合和边缘电容值的方法，其中集成电路包括多层导体， 每个导体具有一个或多个横向边缘。 该方法包括以下步骤：识别每个导体的一个或多个横向边缘; 基于存在于给定侧边缘上方和/或下方的层中的多个导体，将每个导体的横向边缘分段成边缘碎片; 识别与每个边缘片段横向相邻的边缘片段; 计算边缘片段与其每个横向相邻边缘片段之间的一个或多个关系; 检索每个边缘片段的寄生电容数据; 并且使用所检索的寄生电容数据来计算每个边缘片段的一个或多个寄生电容值。 克服现有方法的缺点在于提取的横向耦合电容基于在给定横向导体边缘上方和/或下方运行的导体的存在，并且边缘电容基于给定横向导体边缘和横向相邻导体之间的间隔 边缘。