-
1.发明授权Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions 失效用于处理检查点指令以允许并发执行重叠指令的方法
公开(公告)号：US5495587A
公开(公告)日：1996-02-27
申请号：US263497
申请日：1994-06-21
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译： 一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。 在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。 然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。 因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。
-
公开(公告)号：US5495590A
公开(公告)日：1996-02-27
申请号：US480107
申请日：1995-06-07
CPC分类号： G06F9/3863 , G06F11/1407
摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.
摘要翻译： 一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。 在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。 然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。 因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。
-
3.发明授权System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results 失效用于在出现正确结果后监视和撤销指令超出序列化点执行的系统
公开(公告)号：US5257354A
公开(公告)日：1993-10-26
申请号：US641987
申请日：1991-01-16
CPC分类号： G06F9/3836 , G06F9/3861
摘要： A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and processing was done in a single instant at the moment that the fetches became allowed.
-
4.发明授权公开(公告)号：US06865645B1
公开(公告)日：2005-03-08
申请号：US09677527
申请日：2000-10-02
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0848
摘要： A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
摘要翻译： 一种支持包括使用包括执行单元的中央处理单元来修改多处理器系统中的后续指令的指令的程序的方法，以及指令单元和包括单独指令和操作数高速缓存的多个高速缓存。
-
5.发明授权Read only store as part of cache store for storing frequently used millicode instructions 失效只读存储作为缓存存储的一部分，用于存储常用的millicode指令
公开(公告)号：US5625808A
公开(公告)日：1997-04-29
申请号：US455820
申请日：1995-05-31
申请人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
发明人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
CPC分类号： G06F9/3802 , G06F9/3017
摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.
摘要翻译： 只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。 高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。 当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。 如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。
-
公开(公告)号：US06662296B1
公开(公告)日：2003-12-09
申请号：US09677231
申请日：2000-10-02
申请人： Mark S. Farrell , John S. Liptay , Charles F. Webb
发明人： Mark S. Farrell , John S. Liptay , Charles F. Webb
IPC分类号： G06F926
CPC分类号： G06F9/30094 , G06F9/30145 , G06F9/3017 , G06F9/322
摘要： An exemplary embodiment of the present invention is a method and system for reducing the number of branch instructions required to test combinations of millicode branch points. The method is implemented via a pipe-lined computer processor executing a millicode routine. The processor interrogates a millicode condition code; interrogates a first field of the TMBP instruction, the results of which determine a logical function to be performed on the millicode condition code; interrogates a second field of the TMBP instruction which specifies a first millicode branch point; interrogates a third field of the TMBP instruction, which specifies a second millicode branch point; and sets a millicode condition code based upon the results of the interrogating and used for executing subsequent TMBP instructions or conditional branch instructions.
摘要翻译： 本发明的示例性实施例是用于减少测试毫分支点的组合所需的分支指令的数量的方法和系统。 该方法通过执行millicode例程的管道式计算机处理器来实现。 处理器询问一个millicode条件代码; 询问TMBP指令的第一个字段，其结果确定要对毫代数条件代码执行的逻辑功能; 询问指定第一毫分支点的TMBP指令的第二字段; 询问TMBP指令的第三个字段，其指定第二个毫分支点; 并根据询问的结果设置一个millicode条件代码，并用于执行后续TMBP指令或条件转移指令。
-
公开(公告)号：US06751708B2
公开(公告)日：2004-06-15
申请号：US10042534
申请日：2002-01-09
IPC分类号： G06F1200
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/30181 , G06F9/3838 , G06F12/0875
摘要： A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch instruction, recognizing the line-touch instruction as a type of branch instruction where the branch is not taken, executing the line-touch instruction to fetch a target line from a target address into the instruction cache, and interlocking the execution of the line-touch instruction with the completion of the fetch of the target line in order to prevent execution of the instruction following the line-touch instruction until after the target line has reached the cache.
摘要翻译： 公开了一种用于指示计算系统确保线路存在于指令高速缓存中的方法，所述指令高速缓存包括选择行触摸指令，将线接触指令识别为不采用分支的分支指令的类型，执行 线接触指令，用于从目标地址获取目标行到指令高速缓存中，并且将行触摸指令的执行与目标行的获取完成互锁，以防止执行跟踪行指令之后的指令， 触摸指令，直到目标行到达缓存。
-
公开(公告)号：US5504859A
公开(公告)日：1996-04-02
申请号：US149260
申请日：1993-11-09
CPC分类号： G06F11/1654 , G06F11/10 , G06F11/1008 , G06F11/1076 , G06F11/1407 , G06F11/1641 , G06F11/165
摘要： Error detection and recovery is provided in a processor of small size and which can be integrated on a single chip by providing buffers for both data and processor status codes in order to contain errors until a subsequent check point preferably generated at the termination of each instruction is reached without detection of an error. Retry of an instruction can therefore be initiated using the status and data validated at the termination of the previous check point and without placing error correction processing in any critical path of the processor. Error detection is accomplished by comparing outputs of at least a pair of unchecked processors for both memory access requests and output data and status codes. Input to the processors is subjected to a parity check and parity check bits are generated for memory access requests. Error correcting codes are generated for data and status codes to allow correction of single bit errors during transmission within the processor or at a storage system. When an error is detected, all data which has not been validated, preferably by changing the logical value of a flag bit associated with each code, at the most recently generated check point is erased. Data codes in which the flag bit has been changed may be transferred to a storage system autonomously even after an error has occurred.
摘要翻译： 在小尺寸的处理器中提供错误检测和恢复，并且可以通过为数据和处理器状态代码提供缓冲器来集成在单个芯片上，以便包含错误，直到在每个指令的终止时优选地生成的后续检查点为 到达没有检测到错误。 因此，可以使用在先前检查点终止时验证的状态和数据来启动指令的重试，并且不在处理器的任何关键路径中进行纠错处理。 通过比较两个存储器访问请求和输出数据和状态代码的至少一对未检查处理器的输出来实现错误检测。 对处理器的输入进行奇偶校验，并为存储器访问请求生成奇偶校验位。 为数据和状态代码生成纠错码，以允许在处理器或存储系统内的传输期间校正单个位错误。 当检测到错误时，擦除最近生成的检查点的所有未被验证的数据，优选地通过改变与每个代码相关联的标志位的逻辑值。 即使在发生错误之后，标志位已被改变的数据代码也可以被自动地传送到存储系统。
-
9.发明授权Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries 失效具有用于将指令识别数据写入阵列控制列表的逻辑的计算机系统用于精确的分支后恢复
公开(公告)号：US5134561A
公开(公告)日：1992-07-28
申请号：US435647
申请日：1989-12-05
申请人： John S. Liptay
发明人： John S. Liptay
IPC分类号： G06F9/38 , G11C11/419
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3863 , G11C11/419
摘要： A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration. The register management system may be used in a processor having multiple execution units of different types.
摘要翻译： 寄存器管理系统具有比在建筑系统中命名的更多的用于通用目的的物理寄存器。 重命名系统识别特定物理寄存器作为架构化的可寻址或通用寄存器执行。 提供了一个阵列控制列表（ACL）来监视物理寄存器的分配和状态。 提供解码寄存器分配列表（DRAL）来监视所有架构寄存器的状态和与物理寄存器的对应关系。 备用寄存器分配列表（BRAL）用于保留旧状态信息，而不执行序列和条件分支指令。 物理寄存器可以在执行的不同阶段保留表示内容的各个可寻址寄存器的多个副本。 如果指令执行不正确或在导致需要恢复的问题的条件分支上，则可寻址寄存器状态可能会被恢复。 寄存器管理系统可以用在具有不同类型的多个执行单元的处理器中。
-
公开(公告)号：US4287561A
公开(公告)日：1981-09-01
申请号：US62200
申请日：1979-07-30
申请人： John S. Liptay
发明人： John S. Liptay
CPC分类号： G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3867
摘要： In a data processing system which predecodes and queues a plurality of instructions for sequential presentation to an execution unit, and which includes a plurality of instruction-addressable general registers which can be utilized for temporary data storage or source of address modifying information, an interlock mechanism is provided to detect when an instruction is being decoded which requires use of a general register for address modification, but which register has not yet received new data by execution of an instruction awaiting execution in the queue of instructions. Two fields are associated with each instruction awaiting execution in the instruction queue. They identify one or more of the general registers to be loaded with data by execution of the instruction. Compare logic associated with each register of the instruction queue detects when the general registers identified by the fields in the queue include the general register to be used as address modification data by the instruction presently being decoded. Decoding and address formulation are prevented when the compare exists for any instruction awaiting execution in the queue.
摘要翻译： 在用于对执行单元进行顺序显示的多个指令进行预解码和排队的数据处理系统中，并且包括可用于临时数据存储或地址修改信息源的多个可指令寻址的通用寄存器， 被提供用于检测何时正在解码需要使用通用寄存器进行地址修改的指令，但是哪个寄存器尚未通过执行在指令队列中执行的指令而接收到新的数据。 两个字段与等待在指令队列中执行的每个指令相关联。 它们通过执行指令来识别要加载数据的一个或多个通用寄存器。 与指令队列的每个寄存器相关联的比较逻辑检测由队列中的字段识别的通用寄存器是否包含要由当前正在解码的指令用作地址修改数据的通用寄存器。 当等待队列中执行的任何指令存在比较时，就可以防止解码和地址公式化。
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.026 秒)
