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1.发明授权Read only store as part of cache store for storing frequently used millicode instructions 失效只读存储作为缓存存储的一部分，用于存储常用的millicode指令
公开(公告)号：US5625808A
公开(公告)日：1997-04-29
申请号：US455820
申请日：1995-05-31
申请人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
发明人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
CPC分类号： G06F9/3802 , G06F9/3017
摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.
摘要翻译： 只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。 高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。 当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。 如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。
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公开(公告)号：US06751708B2
公开(公告)日：2004-06-15
申请号：US10042534
申请日：2002-01-09
IPC分类号： G06F1200
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/30181 , G06F9/3838 , G06F12/0875
摘要： A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch instruction, recognizing the line-touch instruction as a type of branch instruction where the branch is not taken, executing the line-touch instruction to fetch a target line from a target address into the instruction cache, and interlocking the execution of the line-touch instruction with the completion of the fetch of the target line in order to prevent execution of the instruction following the line-touch instruction until after the target line has reached the cache.
摘要翻译： 公开了一种用于指示计算系统确保线路存在于指令高速缓存中的方法，所述指令高速缓存包括选择行触摸指令，将线接触指令识别为不采用分支的分支指令的类型，执行 线接触指令，用于从目标地址获取目标行到指令高速缓存中，并且将行触摸指令的执行与目标行的获取完成互锁，以防止执行跟踪行指令之后的指令， 触摸指令，直到目标行到达缓存。
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3.发明授权公开(公告)号：US06865645B1
公开(公告)日：2005-03-08
申请号：US09677527
申请日：2000-10-02
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0848
摘要： A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
摘要翻译： 一种支持包括使用包括执行单元的中央处理单元来修改多处理器系统中的后续指令的指令的程序的方法，以及指令单元和包括单独指令和操作数高速缓存的多个高速缓存。
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公开(公告)号：US06745313B2
公开(公告)日：2004-06-01
申请号：US10042533
申请日：2002-01-09
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/1054 , G06F2212/6024
摘要： A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.
摘要翻译： 公开了一种用于在具有高速缓冲存储器和分支历史表的计算机系统中选择数据的方法，其中该方法包括预测对应于该数据的地址，在高速缓冲存储器中选择预测地址处的数据， 数据，将转换的地址与预测地址进行比较，如果它们不同，则在高速缓冲存储器中的翻译地址处重新选择数据，并将转换的地址附加到分支历史表。
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公开(公告)号：US06671794B1
公开(公告)日：2003-12-30
申请号：US09678226
申请日：2000-10-02
申请人： Bruce C. Giamei , Mark A. Check , John S. Liptay
发明人： Bruce C. Giamei , Mark A. Check , John S. Liptay
IPC分类号： G06F938
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836
摘要： A method and system for detecting address generation interlock in a pipelined data processor is disclosed. The method comprises accumulating a plurality of vectors over a predefined number of processor clock cycles, with subsequent vectors corresponding to subsequent clock cycles; accumulating the status of one or more general registers in the plurality of vectors with the same bit location in each vector of the plurality of vectors corresponding to a particular general register; generating a list of pending general register updates from a logical combination of the plurality of vectors; and determining the existence of address generation interlock from the list of pending general register updates.
摘要翻译： 公开了一种在流水线数据处理器中检测地址生成互锁的方法和系统。 该方法包括在预定数量的处理器时钟周期上累积多个向量，后续矢量对应于随后的时钟周期; 在对应于特定通用寄存器的多个向量中的每个向量中的相同比特位置累积多个向量中的一个或多个通用寄存器的状态; 从所述多个向量的逻辑组合生成待决通用寄存器更新的列表; 并从挂起的通用寄存器更新列表中确定地址生成互锁的存在。
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公开(公告)号：US20090259875A1
公开(公告)日：2009-10-15
申请号：US12488670
申请日：2009-06-22
申请人： Mark A. Check , Mark S. Farrell , Dan F. Greiner , James H. Mulder , Damian L. Osisek , Robert R. Rogers , Timothy J. Slegel , Ronald M. Smith, SR.
发明人： Mark A. Check , Mark S. Farrell , Dan F. Greiner , James H. Mulder , Damian L. Osisek , Robert R. Rogers , Timothy J. Slegel , Ronald M. Smith, SR.
CPC分类号： G06F9/30076 , G06F9/45558 , G06F9/5077 , G06F2009/45579
摘要： Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results.
摘要翻译： 提供两种形式的TOD时钟指令，快速存储时钟和存储时钟。 存储时钟快速指令的执行可能产生与之前的TOD结果完全相同的时间（TOD）结果，但是在时钟运行时执行存储时钟快速指令总是产生唯一的TOD结果。
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7.发明授权Performing a perform timing facility function instruction for synchronizing TOD clocks 有权执行用于同步TOD时钟的执行定时设备功能指令公开(公告)号：US08438415B2
公开(公告)日：2013-05-07
申请号：US13402554
申请日：2012-02-22
CPC分类号： G06F1/14
摘要： A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.
摘要翻译： 一种用于转向具有物理时钟的计算机系统的时钟（TOD）时钟的系统，方法和计算机程序产品，该物理时钟提供用于执行步进到公共振荡器的操作的时基。 该方法包括在处理单元处接收用于改变用于控制处理单元的TOD时钟偏移值的时钟转向速率的请求，定义为开始时间的函数的TOD时钟偏移量， 基本偏移（b）和转向率（r）。 该单元安排下一个开始时间来更新TOD时钟偏移值。 在预定时间更新TOD时钟偏移值（d）后，将TOD时钟偏移值加到物理时钟值（Tr）值，以获得逻辑TOD时钟值（Tb），其中逻辑TOD时钟 值可调节，而不需要调整振荡器的步进速率。
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8.发明申请公开(公告)号：US20120173917A1
公开(公告)日：2012-07-05
申请号：US13402554
申请日：2012-02-22
申请人： Eberhard Engler , Mark S. Farrell , Klaus Meissner , Ronald M. Smith, SR. , Mark A. Check , Evangelyn K. Smith
发明人： Eberhard Engler , Mark S. Farrell , Klaus Meissner , Ronald M. Smith, SR. , Mark A. Check , Evangelyn K. Smith
CPC分类号： G06F1/14
摘要： A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.
摘要翻译： 一种用于转向具有物理时钟的计算机系统的时钟（TOD）时钟的系统，方法和计算机程序产品，该物理时钟提供用于执行步进到公共振荡器的操作的时基。 该方法包括在处理单元处接收用于改变用于控制处理单元的TOD时钟偏移值的时钟转向速率的请求，定义为开始时间的函数的TOD时钟偏移量， 基本偏移（b）和转向率（r）。 该单元安排下一个开始时间来更新TOD时钟偏移值。 在预定时间更新TOD时钟偏移值（d）后，将TOD时钟偏移值加到物理时钟值（Tr）值，以获得逻辑TOD时钟值（Tb），其中逻辑TOD时钟 值可调节，而不需要调整振荡器的步进速率。
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公开(公告)号：US20080071502A1
公开(公告)日：2008-03-20
申请号：US11532172
申请日：2006-09-15
申请人： Mark A. Check , Mark S. Farrell , Dan F. Greiner , James H. Mulder , Damian L. Osisek , Robert R. Rogers , Timothy J. Slegel , Ronald M. Smith , Peter G. Sutton
发明人： Mark A. Check , Mark S. Farrell , Dan F. Greiner , James H. Mulder , Damian L. Osisek , Robert R. Rogers , Timothy J. Slegel , Ronald M. Smith , Peter G. Sutton
IPC分类号： G06F17/40
CPC分类号： G06F9/30003
摘要： A method is provided for obtaining time-of-day (“TOD”) clock records on an information processing system. In accordance with such method, a first instruction is issued for recording a TOD clock value. In response to issuing the first instruction, a truncated version of a first current TOD clock value is obtained and recorded as a first TOD clock record, the first TOD clock value being a first current TOD clock value produced by a TOD clock running continuously on the information processing system. Thereafter, a second instruction is issued. In response to issuing the second instruction, a truncated version of a second current TOD clock value is obtained and recorded as a second TOD clock record, the second current TOD clock value being produced by the TOD clock, and the second TOD clock record being permitted to have the same value as the first TOD clock record.
摘要翻译： 提供了一种用于在信息处理系统上获得时间（“TOD”）时钟记录的方法。 根据这种方法，发出用于记录TOD时钟值的第一指令。 响应于发出第一指令，获得第一当前TOD时钟值的截断版本并将其记录为第一TOD时钟记录，第一TOD时钟值是由TOD时钟上连续运行的TOD时钟产生的第一当前TOD时钟值 信息处理系统。 此后，发出第二条指令。 响应于发出第二指令，获得第二当前TOD时钟值的截断版本并记录为第二TOD时钟记录，第二当前TOD时钟值由TOD时钟产生，并且第二TOD时钟记录被允许 具有与第一个TOD时钟记录相同的值。
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10.发明授权Performing a perform timing facility function instruction for sychronizing TOD clocks 有权执行用于同步TOD时钟的执行定时设备功能指令公开(公告)号：US08135978B2
公开(公告)日：2012-03-13
申请号：US12540261
申请日：2009-08-12
申请人： Eberhard Engler , Mark S. Farrell , Klaus Meissner , Ronald M. Smith, Sr. , Evangelyn K. Smith, legal representative , Mark A. Check
CPC分类号： G06F1/14
摘要： A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function.
摘要翻译： 一种用于执行用于使TOD时钟与其他计算机系统的TOD时钟同步的计算机系统的时间（TOD）时钟的执行定时设备（PTFF）指令的系统，方法和计算机程序产品。 计算机系统包括存储器; 以及与计算机存储器通信的处理器。 处理器能够执行PTFF指令，包括：获得在第一通用寄存器中指定的功能代码，用于识别要执行的查询功能或控制功能中的任何一个的功能代码; 从第二通用寄存器获取参数块的存储器地址; 响应于指定查询功能的功能代码，根据指定的查询功能将计算机系统的定时信息存储在参数块中; 响应于指定控制功能的功能代码，使用从参数块获得的定时信息来执行指定的控制功能; 并设置指示指定功能的结果的条件代码值。
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