利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.014 秒)

    Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions
    1.
    发明授权
    Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions 有权
    用于在没有内存模式限制的系统中存储后台数据的延迟存储数据转发的微处理器和方法

    公开(公告)号：US08468306B2

    公开(公告)日：2013-06-18

    申请号：US12031858

    申请日：2008-02-15

    申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    IPC分类号： G06F9/38

    CPC分类号： G06F12/0804 ,  G06F9/30043

    摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.

    摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。

    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE
    2.
    发明申请
    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
    操作控制作为分支机构的功能

    公开(公告)号：US20110320774A1

    公开(公告)日：2011-12-29

    申请号：US12822379

    申请日：2010-06-24

    申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

    摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

    摘要翻译： 一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

    PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS
    4.
    发明申请
    PROCESSOR AND METHOD FOR STORE DATA FORWARDING IN A SYSTEM WITH NO MEMORY MODEL RESTRICTIONS 有权
    在没有记忆模型限制的系统中存储数据转发的处理器和方法

    公开(公告)号：US20090210679A1

    公开(公告)日：2009-08-20

    申请号：US12031898

    申请日：2008-02-15

    申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

    IPC分类号： G06F9/38

    CPC分类号： G06F12/0855 ,  G06F9/3826 ,  G06F9/3834

    摘要： A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.

    摘要翻译： 流水线微处理器包括用于存储转发的电路，通过执行以下操作：对于每个存储请求以及对高速缓存和存储器之一的写入待处理; 获取至少一个完整数据块的最新值; 将存储请求的存储数据与完整的数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的完整数据块缓冲到存储数据队列中; 对于每个加载请求，其中所述加载请求可能需要至少一个更新的完成的数据块：确定在逐块的基础上存储转发是否适合于所述加载请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 并将所选择的数据块转发到加载请求。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING TRACE DATA
    7.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING TRACE DATA 失效
    方法，用于生成跟踪数据的系统和计算机程序产品

    公开(公告)号：US20090216516A1

    公开(公告)日：2009-08-27

    申请号：US12036430

    申请日：2008-02-25

    申请人： Debbie A. St. Onge ,  Jane H. Bartik ,  Barry W. Krumm ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum

    发明人： Debbie A. St. Onge ,  Jane H. Bartik ,  Barry W. Krumm ,  Erwin Pfeffer ,  Chung-Lung Kevin Shum

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3466 ,  G06F11/3461 ,  G06F2201/885

    摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.

    摘要翻译： 提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。 该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

    METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE
    8.
    发明申请
    METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE 有权
    用于处理自我修改代码的高速缓存的方法和系统

    公开(公告)号：US20090210627A1

    公开(公告)日：2009-08-20

    申请号：US12031923

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F9/3812

    摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.

    摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

    Method and system for handling cache coherency for self-modifying code
    9.
    发明授权
    Method and system for handling cache coherency for self-modifying code 有权
    用于处理缓存一致性的自修改代码的方法和系统

    公开(公告)号：US08015362B2

    公开(公告)日：2011-09-06

    申请号：US12031923

    申请日：2008-02-15

    申请人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    发明人： Gregory W. Alexander ,  Christian Jacobi ,  Barry W. Krumm ,  Chung-Lung Kevin Shum ,  Aaron Tsai

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0848 ,  G06F9/3812

    摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.

    摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

    Read only store as part of cache store for storing frequently used millicode instructions
    10.
    发明授权
    Read only store as part of cache store for storing frequently used millicode instructions 失效
    只读存储作为缓存存储的一部分，用于存储常用的millicode指令

    公开(公告)号：US5625808A

    公开(公告)日：1997-04-29

    申请号：US455820

    申请日：1995-05-31

    申请人： Charles F. Webb ,  Mark S. Farrell ,  Barry W. Krumm ,  John S. Liptay ,  Jennifer S. A. Navarro ,  Steven B. Risch ,  Mark A. Check

    发明人： Charles F. Webb ,  Mark S. Farrell ,  Barry W. Krumm ,  John S. Liptay ,  Jennifer S. A. Navarro ,  Steven B. Risch ,  Mark A. Check

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/22

    CPC分类号： G06F9/3802 ,  G06F9/3017

    摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.

    摘要翻译： 只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。 高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。 当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。 如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。