公开(公告)号：US08809926B2

公开(公告)日：2014-08-19

申请号：US13605275

申请日：2012-09-06

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

IPC分类号： H01L21/02

CPC分类号： H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228

摘要： A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

摘要翻译： 半导体存储器件可以包括衬底上的公共源极区域，衬底和公共源极区域之间的有源图案，面对有源图案的侧壁的栅极图案，栅极图案和有源图案之间的栅极电介质图案， 公共源极区域和有源图案之间的可变电阻图案以及互连线。

公开(公告)号：US20130056812A1

公开(公告)日：2013-03-07

申请号：US13605275

申请日：2012-09-06

申请人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

发明人： Sua Kim ,  Jin Ho Kim ,  Chulwoo Park ,  Sangbo Lee ,  Hongsun Hwang

IPC分类号： H01L29/82

CPC分类号： H01L27/101 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/228

摘要： A semiconductor memory device may include a common source region on a substrate, an active pattern between the substrate and the common source region, a gate pattern facing a sidewall of the active pattern, a gate dielectric pattern between the gate pattern and the active pattern, a variable resistance pattern between the common source region and the active pattern, and an interconnection line.

摘要翻译： 半导体存储器件可以包括衬底上的公共源极区域，衬底和公共源极区域之间的有源图案，面对有源图案的侧壁的栅极图案，栅极图案和有源图案之间的栅极电介质图案， 公共源极区域和有源图案之间的可变电阻图案以及互连线。

公开(公告)号：US08987811B2

公开(公告)日：2015-03-24

申请号：US13588513

申请日：2012-08-17

申请人： Hak-soo Yu ,  Chulwoo Park ,  Hyun-Woo Chung ,  Sua Kim ,  Hyunho Choi ,  Hongsun Hwang

发明人： Hak-soo Yu ,  Chulwoo Park ,  Hyun-Woo Chung ,  Sua Kim ,  Hyunho Choi ,  Hongsun Hwang

IPC分类号： H01L29/66 ,  H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

摘要： According to example embodiments, a semiconductor device includes a plurality of active pillars protruding from a substrate. Each active pillar includes a channel region between upper and lower doped regions. A contact gate electrode faces the channel region and is connected to a word line. The word line extends in a first direction. A bit line is connected to the lower doped region and extends in a second direction. The semiconductor device further includes a string body connection portion that connects the channel region of at least two adjacent active pillars of the plurality of active pillars.

摘要翻译： 根据示例性实施例，半导体器件包括从衬底突出的多个有源柱。 每个有源支柱包括上和下掺杂区之间的沟道区。 接触栅电极面对沟道区并连接到字线。 字线在第一方向延伸。 位线连接到下掺杂区域并沿第二方向延伸。 该半导体器件还包括连接多个有源支柱的至少两个相邻有效支柱的沟道区域的串体连接部分。