Method and apparatus to reduce random yield loss
    1.
    发明申请
    Method and apparatus to reduce random yield loss 有权
    减少随机产量损失的方法和装置

    公开(公告)号:US20070192751A1

    公开(公告)日:2007-08-16

    申请号:US11725007

    申请日:2007-03-16

    IPC分类号: G06F17/50

    摘要: One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine local critical-area-ratios and optimization potentials for a set of wire-segments. The system can then select a wire segment, and compare its local critical-area-ratio with a global critical-area-ratio. Next, the system can use the result of the comparison to determine a layout optimization. The system can then apply the layout optimization to the wire segment to obtain an improved layout.

    摘要翻译: 本发明的一个实施方案提供了减少随机产率损失的系统。 在操作过程中,系统可以接收设计布局。 系统还可以接收与金属区域和空区域中的颗粒密度相关联的加权因子。 接下来,系统可以确定一组线段的局部临界面积比和优化电位。 然后,系统可以选择一个线段,并将其局部临界面积比与全局临界面积比进行比较。 接下来,系统可以使用比较结果来确定布局优化。 然后,系统可以将布局优化应用于线段以获得改进的布局。

    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations
    2.
    发明申请
    Predicting IC manufacturing yield by considering both systematic and random intra-die process variations 有权
    通过考虑系统和随机的模内工艺变化来预测IC制造产量

    公开(公告)号:US20070174797A1

    公开(公告)日:2007-07-26

    申请号:US11339184

    申请日:2006-01-24

    IPC分类号: G06F17/50

    摘要: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

    摘要翻译: 本发明的一个实施例提供了一种系统,其预测半导体晶片内的管芯的制造成品率。 在操作期间,系统首先接收模具的物理布局。 接下来,系统将模具分割成瓦片阵列。 然后,该系统计算质量指示值的系统变化,以基于模具的物理布局描述整个瓦片阵列上的过程参数。 接下来,系统将质量指示参数的随机变量应用于瓦片阵列中的每个瓦片。 最后,系统基于系统变化和随机变量得到了模具的制造成品率。

    Fast evaluation of average critical area for IC layouts
    3.
    发明申请
    Fast evaluation of average critical area for IC layouts 有权
    快速评估IC布局的平均关键区域

    公开(公告)号:US20060095877A1

    公开(公告)日:2006-05-04

    申请号:US10978946

    申请日:2004-11-01

    IPC分类号: G06F17/10 G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    摘要翻译: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC
    4.
    发明申请
    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC 失效
    IC的平均关键区域的快速评估

    公开(公告)号:US20080148196A1

    公开(公告)日:2008-06-19

    申请号:US12032313

    申请日:2008-02-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    摘要翻译: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    Fast evaluation of average critical area for IC layouts
    5.
    发明授权
    Fast evaluation of average critical area for IC layouts 有权
    快速评估IC布局的平均关键区域

    公开(公告)号:US07346865B2

    公开(公告)日:2008-03-18

    申请号:US10978946

    申请日:2004-11-01

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    摘要翻译: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    Fast evaluation of average critical area for IC layouts
    6.
    发明授权
    Fast evaluation of average critical area for IC layouts 有权
    快速评估IC布局的平均关键区域

    公开(公告)号:US08205185B2

    公开(公告)日:2012-06-19

    申请号:US12542625

    申请日:2009-08-17

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    摘要翻译: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    Fast evaluation of average critical area for IC layouts
    7.
    发明授权
    Fast evaluation of average critical area for IC layouts 失效
    快速评估IC布局的平均关键区域

    公开(公告)号:US07962882B2

    公开(公告)日:2011-06-14

    申请号:US12032313

    申请日:2008-02-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    摘要翻译: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计数由于感兴趣的对象片段而产生的所有关键区域一次。

    ELECTROSTATIC-DISCHARGE PROTECTION USING A MICRO-ELECTROMECHANICAL-SYSTEM SWITCH
    8.
    发明申请
    ELECTROSTATIC-DISCHARGE PROTECTION USING A MICRO-ELECTROMECHANICAL-SYSTEM SWITCH 有权
    使用微机电系统开关进行静电放电保护

    公开(公告)号:US20100014199A1

    公开(公告)日:2010-01-21

    申请号:US12176801

    申请日:2008-07-21

    IPC分类号: H02H9/04 G06F17/50

    CPC分类号: H01L27/0251 H01H59/0009

    摘要: Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.

    摘要翻译: 描述接口电路的实施例。 该接口电路包括具有三个端子的输入焊盘,控制节点和晶体管。 第一端子电耦合到输入焊盘,并且第二端子电耦合到控制节点。 此外,接口电路包括微机电系统(MEMS)开关,其电耦合到输入焊盘和控制节点,其中MEMS开关与晶体管并联。 在没有施加到MEMS开关的控制端子的电压的情况下,MEMS开关闭合,从而电耦合输入焊盘和控制节点。 此外,当将电压施加到MEMS开关的控制端子时,MEMS开关断开,由此使输入焊盘和控制节点电耦合。

    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS
    9.
    发明申请
    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS 有权
    快速评估IC LAYOUTS的平均关键区域

    公开(公告)号:US20090307641A1

    公开(公告)日:2009-12-10

    申请号:US12542625

    申请日:2009-08-17

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

    摘要翻译: 用于近似布局或布局区域的平均临界区域的方法和装置,涉及在感兴趣的所有对象段上求和相应于依赖于对象的特定布局参数的关键区域贡献值,每个贡献值是代表性的 并且被定义为使得对于多个缺陷尺寸中的每个缺陷尺寸,并且对于特定缺陷类型,贡献值集合地计算由于感兴趣的对象片段而产生的所有关键区域一次。

    FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC

    公开(公告)号:US20080216028A1

    公开(公告)日:2008-09-04

    申请号:US12032299

    申请日:2008-02-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.