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公开(公告)号：US06535512B1
公开(公告)日：2003-03-18
申请号：US08614803
申请日：1996-03-07
Applicant: Thomas Daniel , Dieter Nattkemper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkemper , Subir Varma
IPC: H04L1256
CPC classification number: H04L12/5601 , H04L2012/5615 , H04L2012/5618
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
Abstract translation: 异步传输模式（ATM）数字电子通信系统包括ATM通信系统互连和终端单元（ATMCSI / TU）。 该ATMCSI / TU包括可编程微处理器和几个硬件实现的协处理器。 硬件实现的协处理器在微处理器的控制下，专用于执行重复任务。 因此，除了执行与ATM系统中的数字数据包（即，CS-PDU）的实际通信相关联的任务之外，微处理器被释放以执行ATM中的监督任务。 因此，APU被免除执行重复的数据操作任务，而这些任务由使用存储器映射的数据结构和链接的数据列表的一个或多个硬件实现的协处理器执行。
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公开(公告)号：US5848068A
公开(公告)日：1998-12-08
申请号：US614804
申请日：1996-03-07
Applicant: Thomas Daniel , Dieter Nattkemper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkemper , Subir Varma
CPC classification number: H04Q11/0478 , H04L2012/5653
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
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3.发明授权公开(公告)号：US06373846B1
公开(公告)日：2002-04-16
申请号：US09036966
申请日：1998-03-09
Applicant: Thomas Daniel , Dieter Nattkemper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkemper , Subir Varma
IPC: H04L1256
CPC classification number: H04Q11/0478 , H04L2012/5616 , H04L2012/5652
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing respective data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
Abstract translation: 异步传输模式（ATM）数字电子通信系统包括ATM通信系统互连和终端单元（ATMCSI / TU）。 该ATMCSI / TU包括可编程微处理器和几个硬件实现的协处理器。 硬件实现的协处理器在微处理器的控制下，专用于执行重复任务。 因此，除了执行与ATM系统中的数字数据包（即，CS-PDU）的实际通信相关联的任务之外，微处理器被释放以执行ATM中的监督任务。 因此，APU被免除执行相应的数据操作任务，而这些任务由使用存储器映射的数据结构和链接的数据列表的一个或多个硬件实现的协处理器执行。
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公开(公告)号：US5831980A
公开(公告)日：1998-11-03
申请号：US710207
申请日：1996-09-13
Applicant: Subir Varma , Thomas Daniel
Inventor： Subir Varma , Thomas Daniel
CPC classification number: H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/203 , H04Q11/0478 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
Abstract: A shared memory fabric architecture for asynchronous transfer mode (ATM) switches including a multi-dimensional array of electrically interconnected N*M switch modules, where N>>M. The fabric architecture also includes input ports for providing cells to the array of switch modules. The input ports operate at a predetermined speed S. The fabric architecture additionally includes memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module. The memory devices include on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y
Abstract translation: 一种用于异步传输模式（ATM）交换机的共享存储器架构架构，其包括电互连N * M开关模块的多维阵列，其中N >> M。 结构体系结构还包括用于向交换机模块阵列提供小区的输入端口。 输入端口以预定速度S工作。该结构架构另外包括电连接到阵列的存储器件，以在每个开关模块处提供分层存储器结构。 存储器件包括以N * S的高速存储器速度工作的片上高速存储器件和以（Y + M）*的低速存储器速度工作的片外低速存储器件， S，其中Y << N。
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公开(公告)号：US5841772A
公开(公告)日：1998-11-24
申请号：US612194
申请日：1996-03-07
Applicant: Thomas Daniel , Dieter Nattkemper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkemper , Subir Varma
CPC classification number: H04L12/5602 , H04Q11/0478 , H04L2012/5658 , H04L2012/5679
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
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Patent Agency Ranking
公开(公告)号：US5726985A
公开(公告)日：1998-03-10
申请号：US612373
申请日：1996-03-07
Applicant: Thomas Daniel , Dieter Nattkamper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkamper , Subir Varma
CPC classification number: H04L12/5601 , H04L49/3081 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047 , H04Q11/0478 , H04L2012/5615 , H04L2012/5652 , H04L2012/5665
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
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7.发明授权
公开(公告)号：US5621773A
公开(公告)日：1997-04-15
申请号：US611327
申请日：1996-03-08
Applicant: Subir Varma , Thomas Daniel , Dieter Nattkemper
Inventor： Subir Varma , Thomas Daniel , Dieter Nattkemper
CPC classification number: H04J3/0608
Abstract: A T1 digital PCM signal frame synchronizer includes a RAM memory for storing a complete extended superframe of received data, a pattern detector for detecting patterns in the memory that match a predetermined frame alignment signal, and a plurality of address pointer registers and associated counters. A given address within the RAM corresponds to a particular bit position within the received data. The first time that a pattern is detected at a given address within memory, that address is stored into a register, and its associated counter set to one. Subsequent pattern matches and violations at that address cause the counter to increment and decrement, respectively. A register whose counter value decrements down to zero becomes available for storing a new address. In-sync is declared when any counter exceeds an in-sync threshold. Out-of-sync is declared when that counter falls to an out-of-sync threshold or below. The synchronizer continues to search for alternative candidates even after synchronization is declared. When the number of registers provided is limited, initial synchronization speed is increased by storing the address for only every other pattern match for the first three extended superframes of received data, thus ensuring that the pattern matches initially recorded will be more evenly distributed throughout the extended superframe of received data.
Abstract translation: T1数字PCM信号帧同步器包括用于存储接收数据的完整扩展超帧的RAM存储器，用于检测与预定帧对准信号匹配的存储器中的图案的模式检测器，以及多个地址指针寄存器和相关联的计数器。 RAM内的给定地址对应于接收数据内的特定位位置。 第一次在存储器内的给定地址处检测到模式，该地址被存储到寄存器中，并且其相关联的计数器设置为1。 在该地址的后续模式匹配和违规会导致计数器分别递增和递减。 计数器值递减到零的寄存器可用于存储新地址。 当任何计数器超过同步阈值时，同步声明。 当该计数器下降到不同步阈值以下时，将声明不同步。 即使在同步声明之后，同步器继续搜索替代候选。 当提供的寄存器数量有限时，通过仅存储接收数据的前三个扩展超帧的每隔一个模式匹配的地址来增加初始同步速度，从而确保最初记录的模式匹配将更均匀地分布在整个扩展 接收数据的超帧。
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公开(公告)号：US5982749A
公开(公告)日：1999-11-09
申请号：US612112
申请日：1996-03-07
Applicant: Thomas Daniel , Dieter Nattkemper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkemper , Subir Varma
CPC classification number: H04Q11/0478 , H04L2012/5616 , H04L2012/5652 , H04L2012/5679 , H04L2012/5681
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
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9.发明授权Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture 失效ATM交换机的调度器设计及其在分布式共享存储器架构中的实现
公开(公告)号：US5959993A
公开(公告)日：1999-09-28
申请号：US714005
申请日：1996-09-13
Applicant: Subir Varma , Thomas Daniel
Inventor： Subir Varma , Thomas Daniel
CPC classification number: H04L49/30 , H04L49/103 , H04L49/107 , H04L49/20 , H04L49/3081 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
Abstract: A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.
Abstract translation: 一种用于分布式共享存储器交换机架构的小区调度器，其包括用于根据若干不同调度模式之一调度来自交换机结构的输出队列的小区的传输的控制器。 控制器接收模式选择输入，将输出队列隔离成组，为组分配优先级排序，并根据模式选择输入和优先级排序确定每组输出队列中的调度规则之一。 输出队列组包括一组每个虚拟通道（VC）队列和至少一组先入先出（FIFO）队列。 调度规则包括控制器在每个VC队列组中应用的加权公平排队（WFQ）调度规则，以及控制器在至少一组FIFO队列中应用的循环（RR）调度规则。 优先级排名包括分配给每个VC队列组的最高优先级排名。
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公开(公告)号：US5920561A
公开(公告)日：1999-07-06
申请号：US614806
申请日：1996-03-07
Applicant: Thomas Daniel , Dieter Nattkemper , Subir Varma
Inventor： Thomas Daniel , Dieter Nattkemper , Subir Varma
CPC classification number: H04Q11/0478 , H04L2012/5616
Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.
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