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    Semiconductor Memory Devices Having Variable Resistor And Methods Of Fabricating The Same
    1.
    发明申请
    Semiconductor Memory Devices Having Variable Resistor And Methods Of Fabricating The Same 有权
    具有可变电阻器的半导体存储器件及其制造方法

    公开(公告)号：US20120091422A1

    公开(公告)日：2012-04-19

    申请号：US13221242

    申请日：2011-08-30

    申请人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

    发明人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06

    摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening foamed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

    摘要翻译： 根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。 半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。 接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。 可变电阻器可以设置在通过第二区域中的模具电介质层发泡的模制开口中。 接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

    Semiconductor memory devices having variable resistor and methods of fabricating the same
    2.
    发明授权
    Semiconductor memory devices having variable resistor and methods of fabricating the same 有权
    具有可变电阻器的半导体存储器件及其制造方法

    公开(公告)号：US08766232B2

    公开(公告)日：2014-07-01

    申请号：US13221242

    申请日：2011-08-30

    申请人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

    发明人： Sukhun Choi ,  Boun Yoon ,  Kevin Ahn ,  Doo-Sung Yun

    IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06

    摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.

    摘要翻译： 根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。 半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。 接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。 可变电阻器可以设置在通过第二区域中的模具电介质层形成的模具开口中。 接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

    Methods of fabricating a semiconductor device including metal gate electrodes
    3.
    发明授权
    Methods of fabricating a semiconductor device including metal gate electrodes 有权
    制造包括金属栅电极的半导体器件的方法

    公开(公告)号：US08946026B2

    公开(公告)日：2015-02-03

    申请号：US13238284

    申请日：2011-09-21

    申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

    摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES
    6.
    发明申请
    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES 有权
    制造包括金属栅极电极的半导体器件的方法

    公开(公告)号：US20120129331A1

    公开(公告)日：2012-05-24

    申请号：US13238284

    申请日：2011-09-21

    申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

    摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

    Method for fabricating semiconductor devices
    9.
    发明授权
    Method for fabricating semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08268710B2

    公开(公告)日：2012-09-18

    申请号：US12703071

    申请日：2010-02-09

    申请人： Byoungho Kwon ,  Boun Yoon ,  Daeik Kim ,  Sung-Min Cho

    发明人： Byoungho Kwon ,  Boun Yoon ,  Daeik Kim ,  Sung-Min Cho

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/28123 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11575

    摘要： A method for fabricating a semiconductor device includes providing a semiconductor substrate including a memory cell region and peripheral circuit regions. Gate electrodes including gate conductive patterns and capping patterns are formed on the memory cell region and the peripheral circuit regions. An interlayer dielectric covering the gate electrodes is formed. The interlayer dielectric is patterned to form first contact holes exposing the semiconductor substrate along side of the gate electrode in the memory cell region and second contact holes exposing a portion of the capping pattern in the peripheral circuit region such that a bottom surface of the second contact hole is spaced apart from a top surface of the gate conductive pattern. A first plug conductive layer is filled in the first contact holes and a second plug conductive layer is filled in the second contact holes. A planarizing process is performed to expose the capping patterns such that first contact plugs are formed in the memory cell region and second contact plugs are formed in the peripheral circuit region.

    摘要翻译： 一种制造半导体器件的方法包括提供包括存储单元区域和外围电路区域的半导体衬底。 包括栅极导电图案和封盖图案的栅电极形成在存储单元区域和外围电路区域上。 形成覆盖栅电极的层间电介质。 图案化层间电介质以形成沿着存储单元区域中的栅极电极的侧面暴露半导体衬底的第一接触孔，以及露出外围电路区域中的封盖图案的一部分的第二接触孔，使得第二接触件的底表面 孔与栅极导电图案的顶表面间隔开。 第一插头导电层填充在第一接触孔中，第二插头导电层填充在第二接触孔中。 执行平面化处理以暴露封盖图案，使得在存储单元区域中形成第一接触插塞，并且在外围电路区域中形成第二接触插塞。

    Methods of forming CMOS transistors with high conductivity gate electrodes
    10.
    发明授权
    Methods of forming CMOS transistors with high conductivity gate electrodes 有权
    用高电导率栅电极形成CMOS晶体管的方法

    公开(公告)号：US08252675B2

    公开(公告)日：2012-08-28

    申请号：US12942763

    申请日：2010-11-09

    申请人： Jongwon Lee ,  Boun Yoon ,  Sang Yeob Han ,  Chae Lyoung Kim

    发明人： Jongwon Lee ,  Boun Yoon ,  Sang Yeob Han ,  Chae Lyoung Kim

    IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/88 ,  H01L21/4763

    CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

    摘要： Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.

    摘要翻译： 提供一种用于制造MOS晶体管的方法。 该方法包括提供具有第一有源区和第二有源区的衬底; 在所述第一有源区和所述第二有源区上形成虚设栅极叠层，所述伪栅叠层包括栅介电层和虚栅极; 在所述第一有源区中形成源极/漏极区域和设置在所述伪栅极堆叠的两侧的所述第二有源区域; 在源/漏区上形成模绝缘层; 去除所述第一有源区上的所述伪栅电极以在所述模绝缘层上形成第一沟槽; 形成第一金属图案以在所述第一沟槽的下部形成第二沟槽，以及将所述第二有源区上的所述伪栅电极从所述模绝缘层上的第三沟槽移除; 以及在所述第二沟槽和所述第三沟槽中形成第二金属层，以在所述第一有源区上形成第一栅电极，在所述第二有源区上形成第二栅电极。