公开(公告)号：US08675404B2

公开(公告)日：2014-03-18

申请号：US13475204

申请日：2012-05-18

申请人： Hyun-Seung Yoo ,  Sung-Joo Hong ,  Seiichi Aritome ,  Seok-Kiu Lee ,  Sung-Kye Park ,  Gyu-Seog Cho ,  Eun-Seok Choi ,  Han-Soo Joo

发明人： Hyun-Seung Yoo ,  Sung-Joo Hong ,  Seiichi Aritome ,  Seok-Kiu Lee ,  Sung-Kye Park ,  Gyu-Seog Cho ,  Eun-Seok Choi ,  Han-Soo Joo

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

摘要翻译： 一种非易失性存储器件的读取方法，包括分别包括一个浮动栅极和两个控制栅极的多个存储器单元，两个控制栅极分别与浮置栅极的两个交替侧相邻设置，并且两个相邻的存储单元共享一个 所述读取方法包括将读取电压施加到所选择的存储器单元的控制栅极，将第二通过电压施加到与所选择的存储器单元的控制栅极不同的存储单元的控制栅极的替代控制栅极，所述存储器单元从控制栅极开始， 所选择的存储单元，以及施加低于第二通过电压的第一通过电压，以从控制栅极开始的第二选择的存储单元开始，将不同于所选存储单元的控制栅极的存储单元的控制栅极交替 。

公开(公告)号：US06737330B2

公开(公告)日：2004-05-18

申请号：US10259872

申请日：2002-09-30

申请人： Sung-Kye Park

发明人： Sung-Kye Park

IPC分类号： H01L2120

CPC分类号： H01L21/76224

摘要： A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

摘要翻译： 公开了一种半导体器件隔离结构及其制造方法。 隔离结构包括形成在隔离区域上以限定有源区的沟槽。 第一，第二和第三绝缘层沉积在沟槽中。 第二绝缘层具有与第一绝缘层和第三绝缘层不同的蚀刻选择比。 与沟槽的侧壁接触的第三绝缘层的边缘部分特征性地不显示任何塌陷。 因此，当提供亚阈值电压时，不会产生驼峰现象。 结果，防止漏电流增加，并且可以防止器件刷新特性恶化。 此外，第三绝缘层覆盖沟槽的顶部边缘部分。 因此，栅极绝缘层（稍后形成）具有足够的厚度。 因此，可以防止屈服电压特性恶化。

公开(公告)号：US06511890B2

公开(公告)日：2003-01-28

申请号：US09421090

申请日：1999-10-19

申请人： Sung-Kye Park ,  Young-Chul Lee

发明人： Sung-Kye Park ,  Young-Chul Lee

IPC分类号： H01L21331

CPC分类号： H01L21/76828 ,  H01L29/6659

摘要： The present invention related to a method of fabricating a semiconductor device which prevents short channel hump due to the moisture in an insulating interlayer. The present invention includes the steps of forming a trench typed field oxide layer defining an active area in a field area of a semiconductor substrate of a first conductive type, forming a gate to the direction of device width wherein a gate oxide layer is inserted between the gate and semiconductor substrate, forming impurity regions in the semiconductor substrate at both sides of the gate by ion implantation with impurities of a second conductive type, forming an insulating interlayer covering the gate on the semiconductor substrate, and removing moisture contained in the insulating interlayer by thermal treatment.

摘要翻译： 本发明涉及一种制造半导体器件的方法，该半导体器件防止由绝缘中间层中的水分导致的短沟道隆起。 本发明包括以下步骤：在第一导电类型的半导体衬底的场区域中形成限定有源区的沟槽型场氧化物层，在器件宽度方向上形成栅极，其中栅氧化层插入在 栅极和半导体衬底，通过具有第二导电类型的杂质的离子注入在栅极两侧的半导体衬底中形成杂质区，形成覆盖半导体衬底上的栅极的绝缘层，以及通过 热处理。

公开(公告)号：US06479361B1

公开(公告)日：2002-11-12

申请号：US09527686

申请日：2000-03-17

申请人： Sung-Kye Park

发明人： Sung-Kye Park

IPC分类号： H01L21331

CPC分类号： H01L21/76224

摘要： A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

摘要翻译： 公开了一种半导体器件隔离结构及其制造方法。 隔离结构包括形成在隔离区域上以限定有源区的沟槽。 第一，第二和第三绝缘层沉积在沟槽中。 第二绝缘层具有与第一绝缘层和第三绝缘层不同的蚀刻选择比。 与沟槽的侧壁接触的第三绝缘层的边缘部分特征性地不显示任何塌陷。 因此，当提供亚阈值电压时，不会产生驼峰现象。 结果，防止漏电流增加，并且可以防止器件刷新特性恶化。 此外，第三绝缘层覆盖沟槽的顶部边缘部分。 因此，栅极绝缘层（稍后形成）具有足够的厚度。 因此，可以防止屈服电压特性恶化。