公开(公告)号：US20060192249A1

公开(公告)日：2006-08-31

申请号：US11396488

申请日：2006-04-03

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66621

摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

摘要翻译： 在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。 在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。 以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

公开(公告)号：US08168492B2

公开(公告)日：2012-05-01

申请号：US12754128

申请日：2010-04-05

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/8238

CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66621

摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

摘要翻译： 在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。 在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。 以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

公开(公告)号：US20100221876A1

公开(公告)日：2010-09-02

申请号：US12754128

申请日：2010-04-05

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Dong-Won Kim ,  Min-Sang Kim ,  Eun-jung Yun

IPC分类号： H01L21/8234 ,  H01L21/86

CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66621

摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

摘要翻译： 在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。 在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。 以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

公开(公告)号：US20060175669A1

公开(公告)日：2006-08-10

申请号：US11339126

申请日：2006-01-25

申请人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795

摘要： Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

摘要翻译： 提供了包括具有金属栅极的FinFET的半导体器件及其制造方法。 半导体器件包括：形成在半导体衬底中并从半导体衬底的表面突出的有源区; 翅片，其包括由有源区域的表面形成的第一和第二突起，并且基于形成在有源区域中的中心沟槽并且使用第一和第二突起的上表面和侧面作为沟道区域彼此平行; 形成在包括所述鳍片的所述有源区域上的栅极绝缘层; 形成在所述栅极绝缘层上的金属栅电极; 形成在所述金属栅电极的侧壁上的栅极间隔; 以及在金属栅电极的两侧旁边的有源区域中形成的源极和漏极。 这里，金属栅电极包括与栅极间隔物和栅极绝缘层接触的阻挡层和形成在阻挡层上的金属层。

公开(公告)号：US20070034973A1

公开(公告)日：2007-02-15

申请号：US11461825

申请日：2006-08-02

申请人： Eun-jung Yun ,  Sung-young Lee ,  Sung-min Kim ,  Dong-gun Park ,  Dong-uk Choi

发明人： Eun-jung Yun ,  Sung-young Lee ,  Sung-min Kim ,  Dong-gun Park ,  Dong-uk Choi

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78612

摘要： Some embodiments of the present invention provide methods and apparatus for operating a transistor including at least one fully depleted channel region in and/or on a substrate. The methods include applying a reverse body bias to the substrate when turning on the transistor. The substrate may be a bulk wafer substrate. The reverse body bias may allow the transistor to turn on while preventing turn on of a parasitic transistor in the substrate.

摘要翻译： 本发明的一些实施例提供了用于操作晶体管的方法和装置，所述晶体管包括在衬底中和/或衬底上的至少一个完全耗尽的沟道区。 所述方法包括在接通晶体管时将反体偏置施加到衬底。 衬底可以是体晶片衬底。 反向偏置可以允许晶体管导通，同时防止衬底中的寄生晶体管的导通。

公开(公告)号：US07037768B2

公开(公告)日：2006-05-02

申请号：US10884749

申请日：2004-07-02

申请人： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

发明人： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/30604

摘要： An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

摘要翻译： 集成电路器件结构可以通过在其上形成具有窗口的植入掩模形成在包括上和下Si层的结构和其间的中间SiGe x层之间形成。 离子通过上部Si层进入植入掩模中通过窗口暴露的中间SiGe层的一部分，并将离子注入到中间SiGe x x的部分中， SUB>层外面的窗口。 蚀刻窗口外部的中间SiGe x X层的部分，并且通过其中注入离子的窗口露出的中间SiGe层的部分基本上不被蚀刻以形成 图案化的中间SiGe x层。

公开(公告)号：US20050003628A1

公开(公告)日：2005-01-06

申请号：US10884749

申请日：2004-07-02

申请人： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

发明人： Eun-jung Yun ,  Sung-young Lee ,  Chang-sub Lee ,  Sung-min Kim ,  Dong-gun Park

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/306 ,  H01L21/76

CPC分类号： H01L21/30604

摘要： An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

摘要翻译： 通过在包括上下Si层和中间SiGex层的结构上形成具有窗口的注入掩模，可以形成集成电路器件结构。 离子通过上部Si层进入植入掩模中通过窗口暴露的中间SiGex层的一部分，并将离子注入到窗口外部的中间SiGex层的部分中。 蚀刻窗口外部的中间SiGex层的部分，并且通过其中注入离子的窗口露出的中间SiGex层的部分基本上不被蚀刻以形成图案化的中间SiGex层。

公开(公告)号：US20080128792A1

公开(公告)日：2008-06-05

申请号：US12014276

申请日：2008-01-15

申请人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

摘要翻译： 半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。 该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层， 第一和第二电荷存储层。 栅电极远离基板延伸超过第一和第二电荷存储层。 该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。 还讨论了相关的制造方法。

公开(公告)号：US07348246B2

公开(公告)日：2008-03-25

申请号：US11268034

申请日：2005-11-07

申请人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

摘要翻译： 半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。 该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层， 第一和第二电荷存储层。 栅电极远离基板延伸超过第一和第二电荷存储层。 该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。 还讨论了相关的制造方法。

公开(公告)号：US20060097310A1

公开(公告)日：2006-05-11

申请号：US11268034

申请日：2005-11-07

申请人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

发明人： Sung-min Kim ,  Dong-won Kim ,  Eun-jung Yun

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

摘要翻译： 半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。 该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层， 第一和第二电荷存储层。 栅电极远离基板延伸超过第一和第二电荷存储层。 该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。 还讨论了相关的制造方法。