摘要:
In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.
摘要:
Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要:
Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要:
Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要:
A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.
摘要:
A flip chip interface circuit for combining two identical semiconductor chips on upper and lower surfaces of an assembling lead frame into one flip chip package includes at least first and second address pads and first and second bonding option pads formed symmetrically on the chips in a mirror type arrangement to each other. The first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips. The first and second input pad selection and chip selection signals are output in response to signals from the first and second address pads and first and second bonding option pads of the chips, the first and second semiconductor chip selection signals are output in response to the first and second input pad and chip selection signals, and an interface enable signal is output in response to the first and second semiconductor chip selection signals.
摘要:
Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要:
Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要:
In one aspect, a non-volatile memory includes a phase-change memory cell array which includes a plurality of normal phase-change memory cells and a plurality of pseudo one-time-programmable (OTP) phase-change memory cells, a write driver which writes data into the normal and pseudo OTP phase-change memory cells of the phase-change memory cell array, and an OTP controller which selectively disables the write driver.
摘要:
A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.