-
1.发明申请Split gate formation with high density plasma (HDP) oxide layer as inter-polysilicon insulation layer 审中-公开用高密度等离子体（HDP）氧化层形成分离栅，作为多晶硅间绝缘层公开(公告)号：US20080150013A1
公开(公告)日：2008-06-26
申请号：US11644344
申请日：2006-12-22
申请人： Sung-Shan Tai , Yong-Zhong Hu , Francois Hebert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , Francois Hebert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses method of for manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译： 本发明公开了一种制造半导体功率器件的方法，该沟槽半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部和底部栅极段之间的多晶硅绝缘层分开。 该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。
-
2.发明授权Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer 有权用高密度等离子体氧化物层制造分裂栅的多晶硅绝缘层的方法公开(公告)号：US08053315B2
公开(公告)日：2011-11-08
申请号：US12589045
申请日：2009-10-16
申请人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译： 本发明公开了一种制造沟槽半导体功率器件的方法，该半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部栅极段和底部栅极段之间的多晶硅绝缘层分开。 该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。
-
3.发明申请Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer 有权用高密度等离子体氧化物层制造分裂栅的多晶硅绝缘层的方法公开(公告)号：US20100099230A1
公开(公告)日：2010-04-22
申请号：US12589045
申请日：2009-10-16
申请人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
发明人： Sung-Shan Tai , Yong-Zhong Hu , François Hébert , Hong Chang , Mengyu Pan , Yingying Lou , Yu Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
摘要翻译： 本发明公开了一种制造沟槽半导体功率器件的方法，该半导体功率器件具有填充在半导体衬底中开口的沟槽的分离栅极，其中，分离栅极由设置在顶部栅极段和底部栅极段之间的多晶硅绝缘层分开。 该方法还包括通过在HDP氧化物沉积工艺之后施加RTP工艺以形成HDP氧化物层的蚀刻速率接近热氧化物的蚀刻速率来形成多晶硅层之间的步骤。
-
-
搜索结果
3 条记录 (耗时 0.027 秒)
