公开(公告)号：US08492831B2

公开(公告)日：2013-07-23

申请号：US12636912

申请日：2009-12-14

申请人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

发明人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

IPC分类号： H01L29/66

CPC分类号： G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

摘要翻译： 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。

公开(公告)号：US20110018036A1

公开(公告)日：2011-01-27

申请号：US12636912

申请日：2009-12-14

申请人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok CHO ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

发明人： Sung-min Hwang ,  Han-soo Kim ,  Won-seok CHO ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

IPC分类号： H01L27/085

CPC分类号： G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

摘要： A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

摘要翻译： 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。

公开(公告)号：US08324675B2

公开(公告)日：2012-12-04

申请号：US12644976

申请日：2009-12-22

申请人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

发明人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.

摘要翻译： 一种具有垂直通道结构的闪速存储器件。 闪速存储装置包括：具有沿第一方向延伸的表面的基板，具有柱状的沟道区域，并且在与第一方向垂直的第二方向上从基板延伸;栅极介电层，形成在沟道区域周围 ，包括在所述第二方向上依次形成在所述沟道区周围的多个晶体管的存储单元串，其中所述栅介质层设置在所述多个晶体管和所述沟道区之间，并且位线连接到所述多个晶体管中的一个晶体管 并且围绕通道区域的一端的侧壁和上表面，以便直接接触通道区域。

公开(公告)号：US20110024816A1

公开(公告)日：2011-02-03

申请号：US12644976

申请日：2009-12-22

申请人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

发明人： Hui-chang Moon ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region.

摘要翻译： 一种具有垂直通道结构的闪速存储器件。 闪速存储装置包括：具有沿第一方向延伸的表面的基板，具有柱状的沟道区域，并且在与第一方向垂直的第二方向上从基板延伸;栅极介电层，形成在沟道区域周围 ，包括在所述第二方向上依次形成在所述沟道区周围的多个晶体管的存储单元串，其中所述栅介质层设置在所述多个晶体管和所述沟道区之间，并且位线连接到所述多个晶体管中的一个晶体管 并且围绕通道区域的一端的侧壁和上表面，以便直接接触通道区域。

公开(公告)号：US08133784B2

公开(公告)日：2012-03-13

申请号：US12588534

申请日：2009-10-19

申请人： Dew-ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

发明人： Dew-ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8236

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.

摘要翻译： 根据示例性实施例的制造非易失性存储器件的方法可以包括蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第一部分的多个第一开口。 可以在多个第一开口中形成多个沟道层，以便涂覆半导体衬底的多个第一部分和多个第一开口的侧表面。 可以在多个通道层上形成多个绝缘柱，以填充多个第一开口。 可以进一步蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第二部分的多个第二开口。 可以通过去除多个牺牲膜来形成多个侧开口。 多个栅极电介质膜可以形成在多个侧面开口的表面上。 可以在多个栅极电介质膜上形成多个栅电极，以填充多个侧开口。

公开(公告)号：US20100248439A1

公开(公告)日：2010-09-30

申请号：US12588534

申请日：2009-10-19

申请人： Dew-Ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

发明人： Dew-Ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.

摘要翻译： 根据示例性实施例的制造非易失性存储器件的方法可以包括蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第一部分的多个第一开口。 可以在多个第一开口中形成多个沟道层，以便涂覆半导体衬底的多个第一部分和多个第一开口的侧表面。 可以在多个通道层上形成多个绝缘柱，以填充多个第一开口。 可以进一步蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第二部分的多个第二开口。 可以通过去除多个牺牲膜来形成多个侧开口。 多个栅极电介质膜可以形成在多个侧面开口的表面上。 可以在多个栅极电介质膜上形成多个栅电极，以填充多个侧开口。

公开(公告)号：US09515341B2

公开(公告)日：2016-12-06

申请号：US13585472

申请日：2012-08-14

申请人： Seong-woo Choi ,  Jong-chan Lee ,  Ki-hyun Kim ,  Sung-kon Kim ,  Pil-won Heo ,  Ki-hyun Kim

发明人： Seong-woo Choi ,  Jong-chan Lee ,  Ki-hyun Kim ,  Sung-kon Kim ,  Pil-won Heo ,  Ki-hyun Kim

IPC分类号： H01M8/10 ,  C08J5/22

CPC分类号： H01M8/103 ,  C08J5/22 ,  C08J2379/06 ,  H01M8/1044 ,  H01M8/1051 ,  H01M8/1072 ,  H01M8/1081 ,  H01M2300/0082 ,  H01M2300/0091 ,  Y02E60/521 ,  Y02P70/56

摘要： A porous membrane with pores that includes a polymerization product of a polyazole-based material, an electrolyte membrane including the porous membrane with a proton-conductive polymer provided in pores of the porous membrane, methods of manufacturing the porous membrane and the electrolyte membrane, and a fuel cell employing at least one of the porous membrane and the electrolyte membrane.

摘要翻译： 一种具有孔的多孔膜，其包含聚唑类材料的聚合产物，包含多孔膜的多孔膜和设置在多孔膜的孔中的质子传导性聚合物的电解质膜，制造多孔膜和电解质膜的方法，以及 使用多孔膜和电解质膜中的至少一种的燃料电池。

公开(公告)号：US20130045436A1

公开(公告)日：2013-02-21

申请号：US13585472

申请日：2012-08-14

申请人： Seong-woo Choi ,  Jong-chan Lee ,  Ki-hyun Kim ,  Sung-kon Kim ,  Pil-won Heo ,  Ki-Hyun Kim

发明人： Seong-woo Choi ,  Jong-chan Lee ,  Ki-hyun Kim ,  Sung-kon Kim ,  Pil-won Heo ,  Ki-Hyun Kim

IPC分类号： H01M8/10 ,  B05D5/12 ,  C08J5/22

CPC分类号： H01M8/103 ,  C08J5/22 ,  C08J2379/06 ,  H01M8/1044 ,  H01M8/1051 ,  H01M8/1072 ,  H01M8/1081 ,  H01M2300/0082 ,  H01M2300/0091 ,  Y02E60/521 ,  Y02P70/56

摘要： A porous membrane with pores that includes a polymerization product of a polyazole-based material, an electrolyte membrane including the porous membrane with a proton-conductive polymer provided in pores of the porous membrane, methods of manufacturing the porous membrane and the electrolyte membrane, and a fuel cell employing at least one of the porous membrane and the electrolyte membrane.

摘要翻译： 一种具有孔的多孔膜，其包含聚唑类材料的聚合产物，包含多孔膜的多孔膜和设置在多孔膜的孔中的质子传导性聚合物的电解质膜，制造多孔膜和电解质膜的方法，以及 使用多孔膜和电解质膜中的至少一种的燃料电池。

公开(公告)号：US08426272B2

公开(公告)日：2013-04-23

申请号：US13545711

申请日：2012-07-10

申请人： Young-bae Yoon ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

发明人： Young-bae Yoon ,  Jeong-dong Choe ,  Hee-soo Kang ,  Dong-hoon Jang ,  Ki-hyun Kim

IPC分类号： H01L21/8247

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11548

摘要： Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

公开(公告)号：US07616135B2

公开(公告)日：2009-11-10

申请号：US12027317

申请日：2008-02-07

申请人： Jae-seong Shim ,  Ki-hyun Kim ,  Hyun-soo Park ,  Kiu-hae Jung ,  Iqbal Mahboob

发明人： Jae-seong Shim ,  Ki-hyun Kim ,  Hyun-soo Park ,  Kiu-hae Jung ,  Iqbal Mahboob

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B2020/1457 ,  H03M5/145 ,  H03M7/46

摘要： A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

摘要翻译： 一种产生和分配码字的方法包括：当前一个码字“a”和随后的码字“b”形成码流X时，将两个可选码字b1和b2之一分配为码字“b”，其中码字b1和b2具有 相反的INV值，其是指示码字中包含的“1”的数目是奇数还是偶数的参数。 当前一个码字“a”的码流和随后的码字b1为X1时，当前一个码字“a”和随后的码字b2的码流为X2时，分配码字，使得X1的INV值 并且当前面的码字“a”或者随后的码字b1（b2）（b1或b2）应该被替换为符合在码字之间给定的预定边界条件的另一码字时，X2被维持为相反。 分配码字使得能够维持码流的DC抑制能力。