公开(公告)号：US10396086B2

公开(公告)日：2019-08-27

申请号：US15639733

申请日：2017-06-30

Applicant: Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

Inventor： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US20160284419A1

公开(公告)日：2016-09-29

申请号：US15176269

申请日：2016-06-08

Applicant: Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract translation: 非易失性存储器件，其操作方法和包括其的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US20150380093A1

公开(公告)日：2015-12-31

申请号：US14849029

申请日：2015-09-09

Applicant: Sun-il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

Inventor： Sun-il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract translation: 非易失性存储器件，其操作方法和包括其的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US08563378B2

公开(公告)日：2013-10-22

申请号：US13238104

申请日：2011-09-21

Applicant: Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

Inventor： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

IPC: H01L21/336

CPC classification number: H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

Abstract translation: 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US08492831B2

公开(公告)日：2013-07-23

申请号：US12636912

申请日：2009-12-14

Applicant: Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

Inventor： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

IPC: H01L29/66

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

Abstract translation: 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。

公开(公告)号：US08222742B2

公开(公告)日：2012-07-17

申请号：US12457290

申请日：2009-06-05

Applicant: Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

Inventor： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

IPC: H01L23/48

CPC classification number: H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

Abstract translation: 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

公开(公告)号：US08168530B2

公开(公告)日：2012-05-01

申请号：US12842703

申请日：2010-07-23

Applicant: Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

Inventor： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC: H01L21/4763

CPC classification number: H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

Abstract translation: 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

公开(公告)号：US20120077320A1

公开(公告)日：2012-03-29

申请号：US13238104

申请日：2011-09-21

Applicant: Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

Inventor： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

IPC: H01L21/336

CPC classification number: H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

Abstract translation: 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层上方，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US20110002178A1

公开(公告)日：2011-01-06

申请号：US12817793

申请日：2010-06-17

Applicant: Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

Inventor： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

IPC: G11C7/00 ,  H01L27/105

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract translation: 提供了具有金属源线的垂直非易失性存储器件。 垂直非易失性存储器件包括形成在半导体衬底的第一部分上且相对于半导体衬底的表面垂直布置的单元串单元，形成在半导体衬底的第二部分之间的细胞串单元 在杂质区上形成的导电线，以及形成在电池串单元的侧壁上的间隔物，并使导电线与电池串单元绝缘。

公开(公告)号：US20100032762A1

公开(公告)日：2010-02-11

申请号：US12536775

申请日：2009-08-06

Applicant: Jun-Beom Park ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jong-In Yun ,  Mi-So Hwang

Inventor： Jun-Beom Park ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jong-In Yun ,  Mi-So Hwang

IPC: H01L27/12

CPC classification number: H01L27/0688 ,  H01L25/0657 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/12 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.

Abstract translation: 提供堆叠型半导体器件及其制造方法。 堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案 上半导体图案。 接触插头的上表面接触半导体图案的下表面。 由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减少。