公开(公告)号：US6160393A

公开(公告)日：2000-12-12

申请号：US418333

申请日：1999-10-14

Applicant: Sung-tae Ahn ,  Yong-jin Jeon

Inventor： Sung-tae Ahn ,  Yong-jin Jeon

IPC: G05F3/24 ,  G05F3/20 ,  G05F3/26 ,  G05F3/16

CPC classification number: G05F3/262

Abstract: A bandgap voltage reference circuit according to the present invention generates a constant reference voltage and is not affected by variations in a power supply voltage and in a manufacturing process. In the bandgap voltage reference circuit, a constant voltage supply unit supplies a constant voltage, a first current mirror mirrors a first current flowing through the constant voltage supply unit to generate a second current, and a second current mirror controlled by the constant voltage from the constant voltage supply unit mirrors the second current to generate a third current and outputs the third current to an output node. A voltage reference unit is connected to the output node to provide a reference voltage to the output node. The voltage reference unit includes at least one PMOS transistor and at least one NMOS transistor which are connected to each other in series or in parallel. Ion implantation processes for determining threshold voltages of the PMOS transistor and the NMOS transistor are simultaneously performed.

Abstract translation: 根据本发明的带隙电压参考电路产生恒定的参考电压，并且不受电源电压的变化和制造过程的影响。 在带隙电压基准电路中，恒定电压供给单元提供恒定电压，第一电流镜反射流过恒压电源单元的第一电流以产生第二电流，以及由来自所述恒定电压的恒定电压控制的第二电流镜 恒压电源单元镜像第二电流以产生第三电流，并将第三电流输出到输出节点。 电压参考单元连接到输出节点以向输出节点提供参考电压。 电压参考单元包括至少一个PMOS晶体管和至少一个NMOS晶体管，它们彼此串联或并联连接。 同时执行用于确定PMOS晶体管和NMOS晶体管的阈值电压的离子注入工艺。