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    Architecture optimizer
    1.
    发明授权
    Architecture optimizer 失效
    架构优化器

    公开(公告)号：US08336017B2

    公开(公告)日：2012-12-18

    申请号：US13008900

    申请日：2011-01-19

    申请人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

    发明人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了系统和方法以自动生成由计算机可读代码或模型描述的定制集成电路（IC）。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过以层次的方式改变架构的一个或多个参数来迭代地优化处理器架构，直到使用架构优化器（AO）满足表示为成本函数的所有定时和硬件约束; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

    ARCHITECTURE OPTIMIZER
    2.
    发明申请
    ARCHITECTURE OPTIMIZER 失效
    架构优化器

    公开(公告)号：US20120185809A1

    公开(公告)日：2012-07-19

    申请号：US13008900

    申请日：2011-01-19

    申请人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

    发明人： Suresh Kadiyala ,  Pius Ng ,  Anand Pandurangam ,  Satish Padmanabhan ,  James Player

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/84

    摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了系统和方法以自动生成由计算机可读代码或模型描述的定制集成电路（IC）。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过以层次的方式改变架构的一个或多个参数来迭代地优化处理器架构，直到使用架构优化器（AO）满足表示为成本函数的所有定时和硬件约束; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

    Application driven power gating
    3.
    发明授权
    Application driven power gating 失效
    应用驱动电源门控

    公开(公告)号：US08589854B2

    公开(公告)日：2013-11-19

    申请号：US12835628

    申请日：2010-07-13

    申请人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

    发明人： Pius Ng ,  Satish Padmanabhan ,  Anand Pandurangan ,  Ananth Durbha ,  Suresh Kadiyala ,  Gary Oblock

    IPC分类号： G06F11/22

    CPC分类号： G06F17/505 ,  G06F2217/78

    摘要： Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用的方式来管理定制集成电路（IC）设计中的电力的系统和方法; 自动生成针对所述计算机可读代码唯一定制的处理器架构，所述处理器架构具有一个或多个处理块和一个或多个电源域; 基于所述代码简档来确定每个处理块是否需要;以及将每个块分配给所述功率域中的一个; 并根据代码简档对功率域进行选通; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

    Intelligent architecture creator
    4.
    发明授权
    Intelligent architecture creator 失效
    智能建筑创作者

    公开(公告)号：US08423929B2

    公开(公告)日：2013-04-16

    申请号：US12906857

    申请日：2010-10-18

    申请人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

    发明人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

    IPC分类号： G06F17/50

    CPC分类号： G06F15/76 ,  G06F17/505 ,  G06F2217/68

    摘要： Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了系统和方法以自动生成由计算机可读代码描述的定制集成电路（IC）的处理器架构。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过改变一个或多个参数来迭代地优化处理器架构，直到满足表示为成本函数的所有定时和硬件约束为止; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

    AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION
    6.
    发明申请
    AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION 审中-公开
    自动优化集成电路发生器从算法和规范

    公开(公告)号：US20130263067A1

    公开(公告)日：2013-10-03

    申请号：US13626878

    申请日：2012-09-25

    申请人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

    发明人： Satish Padmanabhan ,  Pius Ng ,  Anand Pandurangan ,  Suresh Kadiyala ,  Ananth Durbha ,  Tak Shigihara

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5045

    摘要： Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了通过接收定制集成电路的规范来自动设计定制集成电路的系统和方法，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动生成具有可编程处理器的计算机体系结构和用于最适合约束的计算机可读代码的一个或多个协处理器; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

    System, architecture and micro-architecture (SAMA) representation of an integrated circuit
    7.
    发明授权
    System, architecture and micro-architecture (SAMA) representation of an integrated circuit 失效
    集成电路的系统，架构和微架构（SAMA）表示

    公开(公告)号：US08484588B2

    公开(公告)日：2013-07-09

    申请号：US12835631

    申请日：2010-07-13

    申请人： Pius Ng ,  Satish Padmanabhan ,  Suresh Kadiyala

    发明人： Pius Ng ,  Satish Padmanabhan ,  Suresh Kadiyala

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement.

    摘要翻译： 公开了系统和方法，通过接收包括由定制IC执行的计算机可读代码的定制IC的规范来自动生成定制集成电路（IC）设计; 生成作为系统，处理器架构和微架构（SAMA）表示的IC的抽象; 向至少具有架构优化视图，物理设计视图和软件工具视图的数据模型提供SAMA表示; 通过迭代地更新SAMA表示和数据模型来优化处理器架构，以自动生成独特地定制为满足一个或多个约束的计算机可读代码的处理器架构; 以及将生成的架构合成到用于半导体制造的定制集成电路的计算机可读描述中。 前述可以在没有或最少的人参与的情况下完成。

    INTELLIGENT ARCHITECTURE CREATOR
    8.
    发明申请
    INTELLIGENT ARCHITECTURE CREATOR 失效
    智能建筑师

    公开(公告)号：US20120096420A1

    公开(公告)日：2012-04-19

    申请号：US12906857

    申请日：2010-10-18

    申请人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

    发明人： Anand Pandurangan ,  Pius Ng ,  Siva Selvaraj ,  Sanjay Banerjee ,  Ananth Durbha ,  Suresh Kadiyala ,  Satish Padmanabhan

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F15/76 ,  G06F17/505 ,  G06F2217/68

    摘要： Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了系统和方法以自动生成由计算机可读代码描述的定制集成电路（IC）的处理器架构。 IC具有一个或多个时序和硬件限制。 该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过改变一个或多个参数来迭代地优化处理器架构，直到满足表示为成本函数的所有定时和硬件约束为止; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

    Architectural level power-aware optimization and risk mitigation
    10.
    发明授权
    Architectural level power-aware optimization and risk mitigation 失效
    建筑级电力感知优化和风险减轻

    公开(公告)号：US08185862B2

    公开(公告)日：2012-05-22

    申请号：US12835640

    申请日：2010-07-13

    申请人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

    发明人： Ananth Durbha ,  Pius Ng ,  Gary Oblock ,  Suresh Kadiyala ,  Satish Padmanabhan

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5045

    摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.

    摘要翻译： 公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用来自动合成定制集成电路的系统和方法; 自动生成针对所述计算机可读代码独特定制的处理器架构，所述处理器架构具有一个或多个处理块以实现一个或多个指令; 基于代码简档确定指令执行序列，并重新分配指令序列以将操作扩展到IC上的不同块以减少热点; 并将生成的处理器芯片规范合成到用于半导体制造的定制集成电路的计算机可读描述中。