公开(公告)号：US08154935B2

公开(公告)日：2012-04-10

申请号：US12769428

申请日：2010-04-28

申请人： Suresh Natarajan Rajan ,  Keith R Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

发明人： Suresh Natarajan Rajan ,  Keith R Schakel ,  Michael John Sebastian Smith ,  David T. Wang ,  Frederick Daniel Weber

IPC分类号： G11C11/00

CPC分类号： G11C8/18 ,  G11C5/04 ,  G11C7/1066 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40618 ,  G11C29/50012

摘要： A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

摘要翻译： 提供了一种用于将从系统传送的信号延迟到多个存储器电路的系统和方法。 包括与多个存储器电路和系统通信的部件。 这样的组件可操作以从系统接收信号并且在延迟之后将该信号传送到至少一个存储器电路。 在其他实施例中，组件可操作以从至少一个存储器电路接收信号，并在延迟之后将该信号传送到系统。

公开(公告)号：US08089795B2

公开(公告)日：2012-01-03

申请号：US11702981

申请日：2007-02-05

申请人： Suresh N. Rajan ,  Keith R Schakel ,  Michael J. S. Smith ,  David T Wang ,  Frederick Daniel Weber

发明人： Suresh N. Rajan ,  Keith R Schakel ,  Michael J. S. Smith ,  David T Wang ,  Frederick Daniel Weber

IPC分类号： G11C5/06

CPC分类号： G11C11/4093 ,  G06F12/00 ,  G11C5/00 ,  G11C7/10 ,  G11C7/1045 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.

摘要翻译： 包括至少一个存储器堆栈的存储器模块包括多个DRAM集成电路和接口电路。 接口电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为单个DRAM集成电路。 在其他实施例中，存储器模块包括至少一个存储器堆栈和缓冲器集成电路。 耦合到主机系统的缓冲器集成电路将存储器堆栈连接到主机系统，以便将存储器堆栈操作为至少两个DRAM集成电路。 在其他实施例中，接口电路以虚线方式将虚拟地址从主机系统映射到DRAM集成电路的物理地址。 在另一个实施例中，接口电路将来自主机系统的一个或多个虚拟地址组映射到DRAM集成电路的单个地址。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于在DRAM集成电路和主机系统之间转换一个或多个物理参数。 在其他实施例中，缓冲电路将存储器堆栈接口到主机系统，用于配置存储器堆叠中的一个或多个DRAM集成电路。 专利权人和美国专利商标局均不打算在摘要中规定的细节构成对明确陈述这些细节的权利要求的限制。