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    Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting
    1.
    发明授权
    Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting 失效
    使用局部变薄或植入，减少寄生晶体管在基于晶闸管的存储器中的影响

    公开(公告)号：US08174046B1

    公开(公告)日：2012-05-08

    申请号：US11362285

    申请日：2006-02-23

    申请人： Marc Laurent Tarabbia ,  Maxim Ershov ,  Rajesh N. Gupta

    发明人： Marc Laurent Tarabbia ,  Maxim Ershov ,  Rajesh N. Gupta

    IPC分类号： H01L29/74

    CPC分类号： H01L29/66393 ,  H01L27/1027 ,  H01L27/105 ,  H01L29/7436

    摘要： Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.

    摘要翻译： 描述了具有包括基于晶闸管的存储器单元的存储器的集成电路的方法和装置。 一对基于晶闸管的存储单元通常经由位线区域耦合，其中响应于位线区域是共同的，限定了寄生双极结型晶体管。 在另一个实施方案中，一对基于晶闸管的存储单元通常经由阳极区耦合，其中响应于阳极区域是共同的，限定了寄生双极结型晶体管。 公共位线或阳极区域分别具有局部变薄的区域，以通过寄生双极结型晶体管抑制该对之间的电荷转移。 此外，描述了在绝缘体上硅晶片上形成场效应晶体管的方法，其中响应于至少接近绝缘体层的掺杂剂的增加，由寄生双极晶体管促进电荷转移。

    Reduction of electrostatic coupling for a thyristor-based memory cell
    4.
    发明授权
    Reduction of electrostatic coupling for a thyristor-based memory cell 失效
    减少基于晶闸管的存储单元的静电耦合

    公开(公告)号：US08324656B1

    公开(公告)日：2012-12-04

    申请号：US13175676

    申请日：2011-07-01

    申请人： Rajesh N. Gupta ,  Marc Laurent Tarabbia ,  Kevin J. Yang

    发明人： Rajesh N. Gupta ,  Marc Laurent Tarabbia ,  Kevin J. Yang

    IPC分类号： H01L29/74

    CPC分类号： H01L27/1203 ,  G11C11/39 ,  H01L27/1027 ,  H01L29/7436

    摘要： Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.

    摘要翻译： 描述了用于减轻静电耦合的集成电路的实施例。 在一个实施例中，第一栅极电介质分别位于第一有源区上。 第一隔离区分别位于第一活性区之间。 第二栅极电介质分别位于第二有源区上。 第二隔离区域分别位于第二活性区域之间。 在一个实施例中，第一活性区域的高度/厚度比第二活性区域短约20至80％。 在另一个实施例中，第一隔离区域在第一栅极电介质的最上表面上方延伸，同时在第一隔离区域和第一有源区域的侧壁之间提供间隙，以便接收用于形成导电线路的材料。 在另一个实施例中，有源区条纹在p基区和n基区域的宽度分别窄于阴极区和阳极区。

    Configuring flash memory
    6.
    发明授权
    Configuring flash memory 有权
    配置闪存

    公开(公告)号：US07610528B2

    公开(公告)日：2009-10-27

    申请号：US11353873

    申请日：2006-02-14

    申请人： Marc Laurent ,  Frode Milch Pedersen

    发明人： Marc Laurent ,  Frode Milch Pedersen

    IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/16 ,  G11C2029/0401 ,  G11C2029/2602 ,  G11C2029/3602

    摘要： A system for configuring or testing memory may cycle a memory array while substantially concurrently performing other functional testing. In particular implementations, the system may configure, or cycle, a flash memory using a serial interface and test other functional units using the same serial interface substantially concurrently with cycling the flash memory. In some implementations, cycling the flash memory includes erasing and writing to the flash memory in specific patterns in order to dissipate charge that may have accumulated during a fabrication process.

    摘要翻译： 用于配置或测试存储器的系统可以循环存储器阵列，同时基本上同时执行其他功能测试。 在特定实现中，系统可以使用串行接口来配置或循环闪速存储器，并且使用相同的串行接口测试其它功能单元，并且基本上与闪存的循环相同。 在一些实施方案中，循环闪速存储器包括以特定模式擦除和写入闪速存储器，以消散可能在制造过程中累积的电荷。

    Writing to flash memory
    7.
    发明申请
    Writing to flash memory 有权
    写入闪存

    公开(公告)号：US20070192530A1

    公开(公告)日：2007-08-16

    申请号：US11353874

    申请日：2006-02-14

    申请人： Frode Pedersen ,  Marc Laurent

    发明人： Frode Pedersen ,  Marc Laurent

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G11C16/102 ,  G11C2216/14 ,  G11C2216/30

    摘要： Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.

    摘要翻译： 写入闪存的页面可以包括接收基本上独立于闪存的内部架构的写入命令。 在某些实施例中，闪存控制器从遥控器接收两个操作数闪存命令。 在各种实现中，写入过程还可以包括将每个双操作数写入命令转换成依赖于架构的闪存命令; 执行依赖于架构的闪存命令以填充与闪存相关联的页面缓冲器; 随后将页面缓冲器的内容传送到闪存的页面。

    Writing to flash memory
    9.
    发明授权
    Writing to flash memory 有权
    写入闪存

    公开(公告)号：US07428610B2

    公开(公告)日：2008-09-23

    申请号：US11353874

    申请日：2006-02-14

    申请人： Frode Milch Pedersen ,  Marc Laurent

    发明人： Frode Milch Pedersen ,  Marc Laurent

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G11C16/102 ,  G11C2216/14 ,  G11C2216/30

    摘要： Writing to a page of flash memory may include receiving write commands that are substantially independent of an internal architecture of the flash memory. In certain embodiments, two operand flash commands are received at a flash controller from a remote controller. In various implementations, the writing process may further include translating each two-operand write command into architecture-dependent flash commands; executing the architecture-dependent flash commands to fill a page buffer associated with the flash memory; and subsequently transferring contents of the page buffer to the page of flash memory.

    摘要翻译： 写入闪存的页面可以包括接收基本上独立于闪存的内部架构的写入命令。 在某些实施例中，闪存控制器从遥控器接收两个操作数闪存命令。 在各种实现中，写入过程还可以包括将每个双操作数写入命令转换成依赖于架构的闪存命令; 执行依赖于架构的闪存命令以填充与闪存相关联的页面缓冲器; 随后将页面缓冲器的内容传送到闪存的页面。

    Process for automatically detecting the throughput of a network, particularly of the can bus type and for configuring with the detected throughput by transition analysis, and corresponding device
    10.
    发明申请
    Process for automatically detecting the throughput of a network, particularly of the can bus type and for configuring with the detected throughput by transition analysis, and corresponding device 有权
    用于自动检测网络吞吐量的过程，特别是CAN总线类型的吞吐量，以及通过转换分析检测到的吞吐量进行配置，以及相应的设备

    公开(公告)号：US20050180442A1

    公开(公告)日：2005-08-18

    申请号：US11039175

    申请日：2005-01-19

    申请人： Laurentiu Birsan ,  Marc Laurent ,  Thierry Delalande ,  Jean-Sebastien Berthy

    发明人： Laurentiu Birsan ,  Marc Laurent ,  Thierry Delalande ,  Jean-Sebastien Berthy

    IPC分类号： H04L12/24 ,  H04L12/40 ,  H04L12/28

    CPC分类号： H04L12/4135 ,  H04L41/082 ,  H04L41/0869 ,  H04L2012/40215 ,  H04L2012/40273

    摘要： A process for automatically detecting throughput of a network by a device. The network transmits a signal on which messages are carried that include bits of length LBIT and of a dominant or recessive type. The process includes the following successive steps: (a) the device goes into a listen mode; (b) the device obtains a triplet of successive transitions in the signal transmitted on the network, the triplet delimiting a first and second signal level, one dominant and the other recessive; (c) the device measures the duration, expressed as a period TH number of a clock of the device, of each of the first and second levels; (d) as a function of the measured durations of the signal levels, the device obtains a new throughput configuration by determining values for parameters that define the bit length LBIT; (e) the device validates the new throughput configuration; (g) if the device detects that at least one throughput adaptation condition is verified, it goes into a normal mode, otherwise it obtains a next transition of the signal, which delimits with the last previous transition a new level of the signal, it measures the duration of the new level and it reiterates steps (d) to (g) taking account of the new signal level.

    摘要翻译： 用于自动检测设备的网络吞吐量的过程。 网络传送信号，其上携带有包括长度为L / BIT的位和具有显性或隐性类型的位的消息。 该过程包括以下连续步骤：（a）设备进入监听模式; （b）该设备获得在网络上发送的信号中的连续转换的三元组，三重态限定第一和第二信号电平，一个占优势和另一个隐性; （c）所述装置测量所述第一和第二电平中的每一个的所述持续时间，表示为所述装置的时钟的周期T H SUB数; （d）根据测量的信号电平持续时间的函数，器件通过确定定义位长度LIT的参数的值来获得新的吞吐量配置; （e）设备验证新的吞吐量配置; （g）如果设备检测到至少一个吞吐量适应条件被验证，则其进入正常模式，否则它获得信号的下一个转换，该信号的定义与上一次转换一个新的信号水平，其测量 新级别的持续时间，并重申步骤（d）至（g），考虑到新的信号水平。