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1.发明申请EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE SQUARE ROOT CIRCUITS 审中-公开在包括平方根电路的两个或多个电路设计之间的等效检查公开(公告)号：US20160012177A1
公开(公告)日：2016-01-14
申请号：US14860549
申请日：2015-09-21
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Carl P. Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F7/4873 , G06F7/4876 , G06F7/5525 , G06F9/3001 , G06F9/455 , G06F17/50 , G06F17/504
摘要： Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships.
摘要翻译： 描述了用于证明包括一个或多个分割电路和/或一个或多个平方根电路的两个或更多个电路设计之间的等效性的方法和装置。 一些实施例分析电路设计以确定两个分割（或平方根）电路的输入之间的输入关系。 接下来，实施例基于输入关系确定两个分割（或平方根）电路的输出之间的输出关系。 然后，实施例通过使用输入和输出关系来证明电路设计之间的等同性。
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公开(公告)号：US20150213167A1
公开(公告)日：2015-07-30
申请号：US14167716
申请日：2014-01-29
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Per M. Bjesse , Carl P. Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design.
摘要翻译： 描述了在执行电路设计的形式验证时共享感应不变量的方法和装置。 具体来说，一些实施例假定属性的至少一个归纳不变量是真实的，同时证明另一属性。 根据一个定义，属性的感性不变性是归纳断言，使得满足感性断言的所有状态也满足该属性。 根据一个定义，电感断言描述了一组状态，其包括电路设计的所有合法初始状态，并且在对电路设计进行建模的过渡关系下闭合。
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3.发明申请EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE DIVISION AND/OR SQUARE ROOT CIRCUITS 有权两个或更多电路设计之间的等效检查，包括部分和/或平方根电路公开(公告)号：US20140033151A1
公开(公告)日：2014-01-30
申请号：US13665827
申请日：2012-10-31
申请人： SYNOPSYS, INC.
发明人： Himansu Jain , Carl P. Pixley
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F7/4873 , G06F7/4876 , G06F7/5525 , G06F9/3001 , G06F9/455 , G06F17/50 , G06F17/504
摘要： Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships.
摘要翻译： 描述了用于证明包括一个或多个分割电路和/或一个或多个平方根电路的两个或更多个电路设计之间的等效性的方法和装置。 一些实施例分析电路设计以确定两个分割（或平方根）电路的输入之间的输入关系。 接下来，实施例基于输入关系确定两个分割（或平方根）电路的输出之间的输出关系。 然后，实施例通过使用输入和输出关系来证明电路设计之间的等同性。
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4.发明授权Equivalence checking between two or more circuit designs that include division circuits 有权包含分割电路的两个或多个电路设计之间的等效性检查公开(公告)号：US09189581B2
公开(公告)日：2015-11-17
申请号：US13665827
申请日：2012-10-31
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Carl P. Pixley
CPC分类号： G06F17/5081 , G06F7/4873 , G06F7/4876 , G06F7/5525 , G06F9/3001 , G06F9/455 , G06F17/50 , G06F17/504
摘要： Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships.
摘要翻译： 描述了用于证明包括一个或多个分割电路和/或一个或多个平方根电路的两个或更多个电路设计之间的等效性的方法和装置。 一些实施例分析电路设计以确定两个分割（或平方根）电路的输入之间的输入关系。 接下来，实施例基于输入关系确定两个分割（或平方根）电路的输出之间的输出关系。 然后，实施例通过使用输入和输出关系来证明电路设计之间的等同性。
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公开(公告)号：US10325054B2
公开(公告)日：2019-06-18
申请号：US14167716
申请日：2014-01-29
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Per M. Bjesse , Carl P. Pixley
IPC分类号： G06F17/50
摘要： Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design.
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6.发明授权公开(公告)号：US09870442B2
公开(公告)日：2018-01-16
申请号：US14860549
申请日：2015-09-21
申请人： Synopsys, Inc.
发明人： Himanshu Jain , Carl P. Pixley
CPC分类号： G06F17/5081 , G06F7/4873 , G06F7/4876 , G06F7/5525 , G06F9/3001 , G06F9/455 , G06F17/50 , G06F17/504
摘要： Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships.
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