公开(公告)号：US10790013B1

公开(公告)日：2020-09-29

申请号：US16026038

申请日：2018-07-02

申请人： Synopsys, Inc.

发明人： Prashant Dubey ,  Ishita Satishchandra Desai ,  Shivangi Mittal ,  Surya Prakash Gupta ,  Jamil Kawa

IPC分类号： G11C11/419 ,  G11C11/412

摘要： An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.

公开(公告)号：US09602085B2

公开(公告)日：2017-03-21

申请号：US14894323

申请日：2013-11-07

申请人： Synopsys, Inc.

发明人： Prashant Dubey ,  Shivangi Mittal ,  Raushan Kumar Jha

IPC分类号： H03K3/00 ,  H03K3/037 ,  G06F1/12 ,  H04L7/033 ,  H03K3/3562

CPC分类号： H03K3/0375 ,  G06F1/12 ,  H03K3/35625 ,  H04L7/0338

摘要： A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUT1 , DOUT2) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.

公开(公告)号：US20160126936A1

公开(公告)日：2016-05-05

申请号：US14894323

申请日：2013-11-07

申请人： SYNOPSYS, INC.

发明人： Prashant Dubey ,  Shivangi Mittal ,  Raushan Kumar Jha

IPC分类号： H03K3/037 ,  G06F1/12 ,  H03K3/3562

CPC分类号： H03K3/0375 ,  G06F1/12 ,  H03K3/35625 ,  H04L7/0338

摘要： A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1, DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUT1, DOUT2) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.

摘要翻译： 数据存储元件包括具有第一和第二锁存器（LI，L2），错误级（ES）和从级（SLS）的主级（MS）。 基于相对于第一阈值电平（TP1）的输入信号（DATA），第一锁存器（LI）基于时钟信号（CLK，CLKT，CLKB）生成第一逻辑信号（DOUT1）。 基于相对于第二阈值电平（TP2）的输入信号（DATA），第二逻辑信号（DOUT2）基于时钟信号（CLK，CLKT，CLKB）以时钟方式产生（L2）。 第二阈值水平（TP2）与第一阈值水平（TP1）不同。 如果第一和第二逻辑信号（DOUT1，DOUT2）具有相同的逻辑状态，则误差级提供具有第一逻辑状态的误差信号（ER），并且在第二逻辑状态下，它们具有不同的逻辑状态。 当错误信号（ER）具有第一逻辑状态时，从属级（SLS）将数据存储元件的输出值（Q）设置为第一和第二逻辑信号（DOUT1，DOUT2）的公共逻辑状态，以及 保持输出值（Q）不变。