公开(公告)号：US20140148005A1

公开(公告)日：2014-05-29

申请号：US14161986

申请日：2014-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ying LEE ,  Jyu-Horng SHIEH

IPC分类号： H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

摘要： A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.

摘要翻译： 使用镶嵌技术形成半导体器件的方法提供端对端间隔小于60nm而不短路的自对准导电线。 该方法包括使用至少一个牺牲硬掩模层来产生心轴并在心轴中形成空隙。 牺牲硬掩模层形成在有利地是绝缘材料的基材上。 在一些实施例中，另一个硬掩模层也设置在基体材料上并在心轴下方。 垫片材料沿心轴形成并填充空隙。 间隔材料用作掩模，并且执行至少一个蚀刻程序以将间隔物材料的图案转化为基底材料。 图案化的基材包括沟槽和凸起部分。 使用镶嵌技术在沟槽中形成导电特征。

公开(公告)号：US20140127897A1

公开(公告)日：2014-05-08

申请号：US14152093

申请日：2014-01-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ying LEE ,  Jyu-Horng Shieh

IPC分类号： H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects.

摘要翻译： 公开了一种在半导体结构中形成双镶嵌结构的方法。 该方法通常包括使用第一硬掩模蚀刻衬底以形成多个第一沟槽和通孔，形成一组第一导电线和通孔互连，去除第一硬掩模，使用第二硬掩模蚀刻衬底以形成 多个第二沟槽和通孔，以及形成一组第二导线和通孔互连。 至少一些第一导电线分散在一些第二导线之间。 在形成第一导电线之后，在形成第二导线之间并通过互连件之间经由互连，在衬底上使用平坦化工艺。

公开(公告)号：US20150179450A1

公开(公告)日：2015-06-25

申请号：US14636219

申请日：2015-03-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Ying LEE ,  Jyu-Horng SHIEH

IPC分类号： H01L21/033 ,  H01L21/311

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  Y10S438/947

摘要： A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

摘要翻译： 多图案化方法包括：使用第一掩模在衬底上图案化硬掩模层中的至少两个第一开口; 在所述至少两个第一开口中的两个中形成间隔件，每个间隔件在其中具有用于在衬底上图案化相应的第一电路图案的间隔开口，其中每个间隔件限定与所述至少两个第一开口中的相应一个相邻的无图案区域 使用第二掩模在硬掩模层中构图第二电路图案。 第二电路图案位于与所述至少两个第一电路图案相邻的图案自由区域之间并且从其排除。

公开(公告)号：US20140193974A1

公开(公告)日：2014-07-10

申请号：US13737192

申请日：2013-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chia-Ying LEE ,  Jyu-Horng SHIEH

IPC分类号： H01L21/308

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  Y10S438/947

摘要： A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

摘要翻译： 多图案化方法包括：使用第一掩模在衬底上图案化硬掩模层中的至少两个第一开口; 在所述至少两个第一开口中的两个中形成间隔件，每个间隔件在其中具有用于在衬底上图案化相应的第一电路图案的间隔开口，其中每个间隔件限定与所述至少两个第一开口中的相应一个相邻的无图案区域 使用第二掩模在硬掩模层中构图第二电路图案。 第二电路图案位于与所述至少两个第一电路图案相邻的图案自由区域之间并且从其排除。