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    Semiconductor device and manufacturing method thereof
    2.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10170355B2

    公开(公告)日：2019-01-01

    申请号：US15616138

    申请日：2017-06-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Chun Huang ,  Chih-Hsiang Yao ,  Jye-Yen Cheng

    IPC: H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

    Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.

    NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS
    4.
    发明申请
    NOVEL CONDUCTOR LAYOUT TECHNIQUE TO REDUCE STRESS-INDUCED VOID FORMATIONS 有权
    新型导体布局技术，以减少压力诱发的声明

    公开(公告)号：US20130241079A1

    公开(公告)日：2013-09-19

    申请号：US13869844

    申请日：2013-04-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    IPC: H01L23/528 ,  H01L21/768

    CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

    Abstract translation: 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

    Conductor layout technique to reduce stress-induced void formations
    6.
    发明授权
    Conductor layout technique to reduce stress-induced void formations 有权
    导体布置技术，以减少应力引起的空隙形成

    公开(公告)号：US09209079B2

    公开(公告)日：2015-12-08

    申请号：US14486012

    申请日：2014-09-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    IPC: H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. One or multiple notches are designed in the layout on a selective portion of the mask for patterning conductor line. The existence of the notch or notches on the selective portion generates extra stress components within the conductor line than would exist without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

    Abstract translation: 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计一个或多个凹口，用于图案化导体线。 选择部分上的缺口或缺口的存在在导体线内产生额外的应力分量，而不存在缺口。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

    Conductor layout technique to reduce stress-induced void formations
    7.
    发明授权
    Conductor layout technique to reduce stress-induced void formations 有权
    导体布置技术，以减少应力引起的空隙形成

    公开(公告)号：US08836141B2

    公开(公告)日：2014-09-16

    申请号：US13869844

    申请日：2013-04-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    IPC: H01L23/48 ,  H01L23/52

    CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

    Abstract translation: 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

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