公开(公告)号：US20160049397A1

公开(公告)日：2016-02-18

申请号：US14461061

申请日：2014-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Ming-Shan SHIEH ,  Cheng-Long CHEN ,  Wai-Yi LIEN ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/285 ,  H01L21/768 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L29/0676 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers.

Abstract translation: 提供了晶体管，集成电路和制造集成电路的方法。 在各种实施例中，晶体管包括源电极，至少一个半导体沟道，栅电极，漏电极和漏极焊盘。 源电极设置在基板中。 半导体通道基本上垂直于源电极延伸。 栅电极围绕半导体通道。 漏电极设置在半导体通道的顶部。 漏极焊盘设置在漏极电极上，其中漏极焊盘包括多个导电层。

公开(公告)号：US20180277538A1

公开(公告)日：2018-09-27

申请号：US15990271

申请日：2018-05-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Ming-Shan SHIEH ,  Cheng-Long CHEN ,  Wai-Yi LIEN ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L29/0676 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.