公开(公告)号：US20240088027A1

公开(公告)日：2024-03-14

申请号：US18508766

申请日：2023-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chiao-Han LEE ,  Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Hsien-Yuan LIAO ,  Tzu-Jin YEH ,  Ying-Ta LU

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/58 ,  H01L23/64

CPC classification number: H01L23/5227 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/562 ,  H01L23/585 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002

Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.

公开(公告)号：US20190103354A1

公开(公告)日：2019-04-04

申请号：US16207041

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chiao-Han LEE ,  Hsien-Yuan LIAO ,  Ying-Ta LU ,  Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L23/58 ,  H01L23/64

Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.

公开(公告)号：US20150364417A1

公开(公告)日：2015-12-17

申请号：US14303206

申请日：2014-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chiao-Han LEE ,  Hsien-Yuan LIAO ,  Ying-Ta LU ,  Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH

IPC: H01L23/522 ,  H01L23/64 ,  H01L23/58 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/562 ,  H01L23/585 ,  H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.

Abstract translation: 集成电路包括衬底上的电感器和围绕电感器的保护环。 保护环包括沿第一方向延伸的多个第一金属线和沿第二方向延伸的多个第二金属线。 多个第二金属线中的第二金属线分别与多个第一金属线中的至少一个第一金属线耦合。 保护环还包括交错线，其包括多个第一金属线中的至少一个第一金属线和多个第二金属线中的至少一个第二金属线的连接子集。 连接子集外部的多个第一金属线中的第一金属线，连接子集外部的多个第二金属线中的第二金属线，以及交错线围绕电感器。

公开(公告)号：US20240387521A1

公开(公告)日：2024-11-21

申请号：US18788823

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ho-Hsiang CHEN ,  Chi-Hsien LIN ,  Ying-Ta LU ,  Hsien-Yuan LIAO ,  Hsiu-Wen WU ,  Chiao-Han LEE ,  Tzu-Jin YEH

IPC: H01L27/08 ,  H01L29/93

Abstract: A semiconductor device includes a substrate including a well region of a first conductive type; a first gate electrode on the substrate; a second gate electrode on the substrate; a first doped region embedded within the well region and is of the first conductive type, a second doped region embedded within the well region and is of the first conductive type, and a third doped region embedded within the well region and is of the first conductive type; and a first interconnection structure electrically connecting the first gate electrode and the second gate electrode. The first doped region and the second doped region are on opposite sides of the first gate electrode.

公开(公告)号：US20230282644A1

公开(公告)日：2023-09-07

申请号：US17854646

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ho-Hsiang CHEN ,  Chi-Hsien LIN ,  Ying-Ta LU ,  Hsien-Yuan LIAO ,  Hsiu-Wen WU ,  Chiao-Han LEE ,  Tzu-Jin YEH

IPC: H01L27/118 ,  H03F1/26 ,  H01L23/522 ,  H03F1/22 ,  H01L23/528

CPC classification number: H01L27/11807 ,  H03F1/26 ,  H01L23/5226 ,  H03F1/223 ,  H01L23/528 ,  H01L2027/11875 ,  H03F2200/294 ,  H03F2200/451

Abstract: A cell layout design for an integrated circuit. In one embodiment, the integrated circuit includes a dual-gate cell forming two transistors connected with each other via a common source/drain terminal. The dual-gate cell includes an active region, two gate lines extending across the active region, at least one first gate via disposed on one or both of the two gate lines and overlapped with the active region, and second gate vias disposed on one or both of the two gate lines and located outside the active region.

公开(公告)号：US20210358844A1

公开(公告)日：2021-11-18

申请号：US17389795

申请日：2021-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chiao-Han LEE ,  Chi-Hsien LIN ,  Ho-Hsiang CHEN ,  Hsien-Yuan LIAO ,  Tzu-Jin YEH ,  Ying-Ta LU

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/58 ,  H01L23/528 ,  H01L23/00 ,  H01L23/64

Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.