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公开(公告)号：US20230008866A1
公开(公告)日：2023-01-12
申请号：US17466417
申请日：2021-09-03
发明人： Chih-Yu LAI , Chih-Liang CHEN , Chi-Yu LU , Shang-Hsuan CHIU
IPC分类号： H01L23/48 , H01L21/768 , H01L25/065 , H01L27/06 , H01L27/02
摘要： A semiconductor device includes a substrate, a first cell having a first functionality, and a second cell having a second functionality. The first cell includes a first portion on a first side of the substrate, wherein the first portion includes a first conductive element; a second portion on a second side of the substrate, wherein the second portion includes a second conductive element; and a first conductive via extending through the substrate and electrically connecting the first conductive element to the second conductive element. The second cell includes a third portion on the first side of the substrate, wherein the third portion includes a third conductive element; a fourth portion on the second side of the substrate, wherein the fourth portion includes a fourth conductive element; and a second conductive via extending through the substrate and electrically connecting the third conductive element to the fourth conductive element.
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公开(公告)号：US20210082739A1
公开(公告)日：2021-03-18
申请号：US17106876
申请日：2020-11-30
发明人： Jung-Chan YANG , Ting-Wei CHIANG , Cheng-I HUANG , Hui-Zhong ZHUANG , Chi-Yu LU , Stefan RUSU
IPC分类号： H01L21/76 , H01L23/528 , G06F30/394 , H03K19/094
摘要： An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.
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3.发明申请公开(公告)号：US20180096981A1
公开(公告)日：2018-04-05
申请号：US15370418
申请日：2016-12-06
发明人： Mao-Wei CHIU , Ting-Wei CHIANG , Hui-Zhong ZHUANG , Li-Chun TIEN , Chi-Yu LU
IPC分类号： H01L27/02 , H01L23/528 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/66 , H01L23/528 , H01L27/0207
摘要： A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values for a first pitch of standard spare cells based on a second pitch of strap lines of a metallization layer; selecting one member of the possible values set to be the first pitch; and placing standard spare cells into a logic area of the layout according to the first pitch; wherein at least one of the generating, selecting and placing is executed by a processor of a computer.
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公开(公告)号：US20210224460A1
公开(公告)日：2021-07-22
申请号：US17222021
申请日：2021-04-05
发明人： Fong-Yuan CHANG , Jyun-Hao CHANG , Sheng-Hsiung CHEN , Ho Che YU , Lee-Chung LU , Ni-Wan FAN , Po-Hsiang HUANG , Chi-Yu LU , Jeo-Yen LEE
IPC分类号： G06F30/392 , H01L27/118 , G06F30/398 , G06F30/39 , H01L23/538 , H01L27/02
摘要： A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.
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公开(公告)号：US20210089700A1
公开(公告)日：2021-03-25
申请号：US17115436
申请日：2020-12-08
发明人： Chi-Yu LU , Ting-Wei CHIANG , Hui-Zhong ZHUANG , Jerry Chang Jui KAO , Pin-Dai SUE , Jiun-Jia HUANG , Yu-Ti SU , Wei-Hsiang MA
IPC分类号： G06F30/394 , G03F1/70 , G03F1/36 , G06F30/398
摘要： An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.
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6.发明申请公开(公告)号：US20200302101A1
公开(公告)日：2020-09-24
申请号：US16895803
申请日：2020-06-08
发明人： Mao-Wei CHIU , Ting-Wei CHIANG , Hui-Zhong ZHUANG , Li-Chun TIEN , Chi-Yu LU
IPC分类号： G06F30/30 , G06F30/39 , G06F30/392
摘要： A method of manufacturing a semiconductor device (for a layout diagram stored on a non-transitory computer-readable medium) includes generating the layout diagram. The generating the layout diagram includes: placing standard functional cells to partially fill a logic area of the layout diagram according to at least one corresponding schematic design thereby leaving, as unfilled, a spare region in the logic area; selecting a first pitch for additional cells to be placed in the spare region, wherein use of the first pitch minimizes wasted space in the spare region; selecting standard not-yet-programmed (SNYP) spare cells, which are to become at least some of the additional cells, according to the first pitch; and placing the selected SNYP spare cells into the spare region of the layout diagram.
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公开(公告)号：US20190286784A1
公开(公告)日：2019-09-19
申请号：US16299973
申请日：2019-03-12
发明人： Fong-Yuan CHANG , Chin-Chou LIU , Hui-Zhong ZHUANG , Meng-Kai HSU , Pin-Dai SUE , Po-Hsiang HUANG , Yi-Kan CHENG , Chi-Yu LU , Jung-Chou TSAI
IPC分类号： G06F17/50
摘要： A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
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公开(公告)号：US20190147132A1
公开(公告)日：2019-05-16
申请号：US16186788
申请日：2018-11-12
发明人： Mao-Wei CHIU , Ting-Wei CHIANG , Hui-Zhong ZHUANG , Li-Chun TIEN , Chi-Yu LU
IPC分类号： G06F17/50
摘要： A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.
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公开(公告)号：US20180151411A1
公开(公告)日：2018-05-31
申请号：US15643825
申请日：2017-07-07
发明人： Jung-Chan YANG , Ting-Wei CHIANG , Cheng-I HUANG , Hui-Zhong ZHUANG , Chi-Yu LU , Stefan RUSU
IPC分类号： H01L21/76 , H01L23/528 , H03K19/094 , G06F17/50
CPC分类号： H01L21/76 , G06F17/5077 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H03K19/094
摘要： An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.
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公开(公告)号：US20180150589A1
公开(公告)日：2018-05-31
申请号：US15792289
申请日：2017-10-24
发明人： Jung-Chan YANG , Ting-Wei CHIANG , Jerry Chang-Jui KAO , Hui-Zhong ZHUANG , Lee-Chung LU , Li-Chun TIEN , Meng-Hung SHEN , Shang-Chih HSIEH , Chi-Yu LU
IPC分类号： G06F17/50 , H01L27/02 , H01L23/522 , H01L23/528
摘要： An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.
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