公开(公告)号：US20190259771A1

公开(公告)日：2019-08-22

申请号：US16404454

申请日：2019-05-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Ming Chuang ,  Chien-Hsuan Liu ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Hsin-Chi Chen

IPC分类号： H01L27/11521 ,  H01L29/06 ,  H01L29/423 ,  H01L27/11548 ,  H01L23/535 ,  H01L27/11575

摘要： A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

公开(公告)号：US11121141B2

公开(公告)日：2021-09-14

申请号：US16404454

申请日：2019-05-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Ming Chuang ,  Chien-Hsuan Liu ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Hsin-Chi Chen

IPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L27/11548 ,  H01L27/11575 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11565

摘要： A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

公开(公告)号：US10283510B2

公开(公告)日：2019-05-07

申请号：US15707554

申请日：2017-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Ming Chuang ,  Chien-Hsuan Liu ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Hsin-Chi Chen

IPC分类号： H01L27/11 ,  H01L27/11521 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L27/11548 ,  H01L27/11575 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11565

摘要： A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

公开(公告)号：US20240172434A1

公开(公告)日：2024-05-23

申请号：US18429264

申请日：2024-01-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC分类号： H10B41/30 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

CPC分类号： H10B41/30 ,  H01L21/32135 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

摘要： A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

公开(公告)号：US11594449B2

公开(公告)日：2023-02-28

申请号：US17207152

申请日：2021-03-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ming Lee ,  Hung-Che Liao ,  Kun-Tsang Chuang ,  Wei-Chung Lu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02

摘要： A method of making a semiconductor structure includes depositing a first passivation material between adjacent conductive elements on a substrate, wherein a bottommost surface of the first passivation material is coplanar with a bottommost surface of each of the adjacent conductive elements. The method further includes depositing a second passivation material on the substrate, wherein the second passivation material contacts a sidewall of each of the adjacent conductive elements and a sidewall of the first passivation material, a bottommost surface of the second passivation material is coplanar with the bottommost surface of each of the adjacent conductive elements, and the second passivation material is different from the first passivation material.

公开(公告)号：US20180006046A1

公开(公告)日：2018-01-04

申请号：US15707554

申请日：2017-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chiang-Ming Chuang ,  Chien-Hsuan Liu ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Hsin-Chi Chen

IPC分类号： H01L27/11521 ,  H01L29/06 ,  H01L27/11575 ,  H01L27/11548 ,  H01L23/535 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11519 ,  G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/0649 ,  H01L29/42328

摘要： A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.