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45 条记录 (耗时 0.017 秒)

    INPUT AND OUTPUT BLOCKS FOR AN ARRAY OF MEMORY CELLS
    6.
    发明公开
    INPUT AND OUTPUT BLOCKS FOR AN ARRAY OF MEMORY CELLS 审中-公开

    公开(公告)号：US20240098991A1

    公开(公告)日：2024-03-21

    申请号：US18520526

    申请日：2023-11-27

    申请人： Silicon Storage Technology, Inc.

    发明人： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

    IPC分类号： H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

    CPC分类号： H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

    摘要： In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

    DOUBLE PATTERNING METHOD OF MANUFACTURING SELECT GATES AND WORD LINES
    7.
    发明公开
    DOUBLE PATTERNING METHOD OF MANUFACTURING SELECT GATES AND WORD LINES 审中-公开

    公开(公告)号：US20240081056A1

    公开(公告)日：2024-03-07

    申请号：US18139347

    申请日：2023-04-25

    申请人： Powerchip Semiconductor Manufacturing Corporation

    发明人： Yi-Yeh Chuang ,  Zih-Song Wang ,  Li-Ta Chen ,  Shun-Yu Gao

    IPC分类号： H10B41/42 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

    CPC分类号： H10B41/42 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

    摘要： A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.

    Manufacturing method of semiconductor structure and flash memory
    8.
    发明授权
    Manufacturing method of semiconductor structure and flash memory 有权

    公开(公告)号：US11877447B2

    公开(公告)日：2024-01-16

    申请号：US18297659

    申请日：2023-04-10

    申请人： Winbond Electronics Corp.

    发明人： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

    IPC分类号： H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

    CPC分类号： H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

    摘要： Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND FLASH MEMORY
    10.
    发明公开
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND FLASH MEMORY 审中-公开

    公开(公告)号：US20230255026A1

    公开(公告)日：2023-08-10

    申请号：US18297659

    申请日：2023-04-10

    申请人： Winbond Electronics Corp.

    发明人： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

    IPC分类号： H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

    CPC分类号： H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

    摘要： Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.