公开(公告)号：US12075618B2

公开(公告)日：2024-08-27

申请号：US17133395

申请日：2020-12-23

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC分类号： H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC分类号： H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

摘要： Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.

公开(公告)号：US20240188289A1

公开(公告)日：2024-06-06

申请号：US18404204

申请日：2024-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Josh Lin ,  Chia-Ta Hsieh ,  Chen-Ming Huang ,  Chi-Wei Ho

IPC分类号： H10B41/30 ,  H01L21/768 ,  H01L23/485 ,  H01L29/423 ,  H01L29/66 ,  H10B41/10 ,  H10B41/40 ,  H10B41/42

CPC分类号： H10B41/30 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L29/42324 ,  H01L29/6653 ,  H10B41/10 ,  H10B41/40 ,  H10B41/42 ,  H01L23/485 ,  H01L29/6656

摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a first conductive structure over a substrate. A first intermediate sidewall spacer is formed to surround the first conductive structure. A masking material is formed over the substrate and around the first intermediate sidewall spacer. A part of the first intermediate sidewall spacer protrudes outward from the masking material. The part of the first intermediate sidewall spacer that protrudes outward from the masking material is etched to form a first sidewall spacer.

公开(公告)号：US20240147717A1

公开(公告)日：2024-05-02

申请号：US18491226

申请日：2023-10-20

申请人： WINBOND ELECTRONICS CORP.

发明人： Hsin-Hung CHOU ,  Cheng-Shuai LI ,  Kao-Tsair TSAI

IPC分类号： H10B41/42 ,  H10B43/40

CPC分类号： H10B41/42 ,  H10B43/40

摘要： A pick-up structure of a memory device and a method of manufacturing the memory device are provided. The pick-up structure includes pick-up electrode stripes. Each pickup electrode stripe includes a main body portion in the peripheral pick-up region and an extending portion extending from the main body portion to the memory cell region. The extending portion is narrower than the main body portion. The sidewall surface of the extending portion is aligned with the sidewall surface of the main body portion.

公开(公告)号：US20230345717A1

公开(公告)日：2023-10-26

申请号：US18344161

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Ling Shih ,  Yong-Shiuan Tsair

IPC分类号： H01L29/423 ,  H10B41/30 ,  H01L23/528 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311 ,  G11C29/14 ,  H10B41/42 ,  H01L21/28 ,  H01L29/788 ,  H01L21/3213

CPC分类号： H10B41/42 ,  G11C29/14 ,  H01L21/31116 ,  H01L21/32137 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H01L29/66545

摘要： Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.

公开(公告)号：US20240172434A1

公开(公告)日：2024-05-23

申请号：US18429264

申请日：2024-01-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC分类号： H10B41/30 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

CPC分类号： H10B41/30 ,  H01L21/32135 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

摘要： A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

公开(公告)号：US11943921B2

公开(公告)日：2024-03-26

申请号：US17874416

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC分类号： H10B41/44 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/40

CPC分类号： H10B41/44 ,  H01L21/0276 ,  H01L21/28035 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76802 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30

摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

公开(公告)号：US20240098991A1

公开(公告)日：2024-03-21

申请号：US18520526

申请日：2023-11-27

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC分类号： H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC分类号： H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

摘要： In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

公开(公告)号：US20240081056A1

公开(公告)日：2024-03-07

申请号：US18139347

申请日：2023-04-25

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Yi-Yeh Chuang ,  Zih-Song Wang ,  Li-Ta Chen ,  Shun-Yu Gao

IPC分类号： H10B41/42 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC分类号： H10B41/42 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

摘要： A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.

公开(公告)号：US11877447B2

公开(公告)日：2024-01-16

申请号：US18297659

申请日：2023-04-10

申请人： Winbond Electronics Corp.

发明人： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC分类号： H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC分类号： H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

摘要： Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20230389319A1

公开(公告)日：2023-11-30

申请号：US18446579

申请日：2023-08-09

申请人： Kioxia Corporation

发明人： Masaki TSUJI ,  Yoshiaki FUKUZUMI

IPC分类号： H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

CPC分类号： H10B43/27 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

摘要： According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.