公开(公告)号：US20220352319A1

公开(公告)日：2022-11-03

申请号：US17857104

申请日：2022-07-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

摘要： Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

公开(公告)号：US20240250125A1

公开(公告)日：2024-07-25

申请号：US18436052

申请日：2024-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L29/4238 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. The structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.