公开(公告)号：US20240250125A1

公开(公告)日：2024-07-25

申请号：US18436052

申请日：2024-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L29/4238 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. The structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US20230378300A1

公开(公告)日：2023-11-23

申请号：US17864104

申请日：2022-07-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Chih-Ching WANG

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6653 ,  H01L21/31111

摘要： In a method of manufacturing a semiconductor device, a fin structure, in which first and second semiconductor layers are alternately stacked over a substrate, is formed, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers are laterally etched in the source/drain space, a first insulating layer is formed on a sidewall of the source/drain space, the first insulating layer is partially etched, thereby forming a first bottom spacer at a bottom of the source/drain space, a second insulating layer is formed on the sidewall of the source/drain space, the second insulating layer is partially etched, thereby forming inner spacers on end faces of the first semiconductor layers and leaving a part of the second insulating layer as a second bottom spacer at the bottom of the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space.

公开(公告)号：US20220352319A1

公开(公告)日：2022-11-03

申请号：US17857104

申请日：2022-07-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

摘要： Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

公开(公告)号：US20240154015A1

公开(公告)日：2024-05-09

申请号：US18187847

申请日：2023-03-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jui-Lin CHEN ,  Hsin-Wen SU ,  Chih-Ching WANG ,  Chen-Ming LEE ,  Chung-I YANG ,  Yi-Feng TING ,  Jon-Hsu HO ,  Lien-Jung HUNG ,  Ping-Wei WANG

IPC分类号： H01L29/423 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC分类号： H01L29/42392 ,  H01L21/76877 ,  H01L21/823821 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66454 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H10B10/12

摘要： A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

公开(公告)号：US20230020933A1

公开(公告)日：2023-01-19

申请号：US17377796

申请日：2021-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wen-Yuan CHEN ,  Chun-Chung SU ,  Jon-Hsu HO ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC分类号： H01L27/088 ,  H01L21/764

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US20220359657A1

公开(公告)日：2022-11-10

申请号：US17308258

申请日：2021-05-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Kuan-Lun CHENG ,  Wen-Hsing HSIEH

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure a first source/drain region, a second source/drain region, and a gate stack disposed between the first source/drain region and the second source/drain region. The semiconductor device structure also includes a conductive feature disposed below the first source/drain region. The semiconductor device structure also includes a power rail disposed below and in contact with the conductive feature. semiconductor device structure also includes a dielectric layer enclosing the conductive feature, wherein an air gap is formed between the dielectric layer and the conductive feature.

公开(公告)号：US20240113201A1

公开(公告)日：2024-04-04

申请号：US18159625

申请日：2023-01-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Bo-Yu LAI ,  Chung-I YANG ,  Sung-En LIN

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/66553 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

公开(公告)号：US20240038866A1

公开(公告)日：2024-02-01

申请号：US17875975

申请日：2022-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ching WANG ,  Chung-I YANG ,  Wei-Yang LEE ,  Wen-Hsing HSIEH

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/6656

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a nanostructure stack over the substrate. The method includes forming a gate stack over the nanostructure stack and the substrate. The method includes removing the first nanostructure forming a first gap between the substrate and the second nanostructure. The method includes forming a first spacer layer in the first gap and a gate spacer over a sidewall of the gate stack. The method includes partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack. The method includes forming a source/drain structure in the first trench and over the first spacer layer.

公开(公告)号：US20230352594A1

公开(公告)日：2023-11-02

申请号：US17732552

申请日：2022-04-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yen-Sheng LU ,  Chung-Chi WEN ,  Yen-Ting CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Chih-Chiang CHANG ,  Chien-I KUO ,  Yuan-Ching PENG ,  Chih-Ching WANG ,  Wen-Hsing Hsieh ,  Chii-Horng LI ,  Yee-Chia YEO

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

摘要： Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a source/drain feature over a substrate, a plurality of semiconductor layers over the substrate, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a gate dielectric layer in contact with the gate electrode layer, and a cap layer. The cap layer has a first portion disposed between the plurality of semiconductor layers and the source/drain feature and a second portion extending outwardly from opposing ends of the first portion. The semiconductor device structure further includes a dielectric spacer disposed between and in contact with the source/drain feature and the second portion of the cap layer.

公开(公告)号：US20230246026A1

公开(公告)日：2023-08-03

申请号：US18132924

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Chun-Chung SU ,  Chung-Wei WU ,  Jon-Hsu HO ,  Kuan-Lun CHENG ,  Wen-Hsing HSIEH ,  Wen-Yuan CHEN ,  Zhi-Qiang WU

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/06

CPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0847

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.