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公开(公告)号：US20220254678A1
公开(公告)日：2022-08-11
申请号：US17729429
申请日：2022-04-26
发明人： Hsin-Yen Huang , Chi-Lin Teng , Hai-Ching Chen , Shau-Lin Shue , Shao-Kuan Lee , Cheng-Chin Lee , Ting-Ya Lo
IPC分类号： H01L21/768 , H01L23/532
摘要： Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.
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公开(公告)号：US11640928B2
公开(公告)日：2023-05-02
申请号：US17412423
申请日：2021-08-26
IPC分类号： H01L21/48 , H01L23/48 , H01L23/52 , H01L23/367 , H01L23/522 , H01L23/373
摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.
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公开(公告)号：US11557511B2
公开(公告)日：2023-01-17
申请号：US17146821
申请日：2021-01-12
发明人： Hsin-Yen Huang , Ting-Ya Lo , Shao-Kuan Lee , Chi-Lin Teng , Cheng-Chin Lee , Hsiaokang Chang , Shau-Lin Shue
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.
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公开(公告)号：US20220359385A1
公开(公告)日：2022-11-10
申请号：US17873214
申请日：2022-07-26
发明人： Shao-Kuan Lee , Hsin-Yen Huang , Cheng-Chin Lee , Kuang-Wei Yang , Ting-Ya Lo , Chi-Lin Teng , Hsiao-Kang Chang , Shau-Lin Shue
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.
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公开(公告)号：US20230068892A1
公开(公告)日：2023-03-02
申请号：US17412403
申请日：2021-08-26
发明人： Hsin-Yen Huang , Ting-Ya Lo , Shao-Kuan Lee , Chi-Lin Teng , Cheng-Chin Lee , Shau-Lin Shue , Hsiao-Kang Chang
IPC分类号： H01L23/522 , H01L21/768
摘要： Some embodiments of the present disclosure relate to an integrated chip, including a semiconductor substrate and a dielectric layer disposed over the semiconductor substrate. A pair of metal lines are disposed over the dielectric layer and laterally spaced apart from one another by a cavity. A barrier layer structure extends along nearest neighboring sidewalls of the pair of metal lines such that the cavity is defined by inner sidewalls of the barrier layer structure and a top surface of the dielectric layer.
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公开(公告)号：US20220293512A1
公开(公告)日：2022-09-15
申请号：US17829590
申请日：2022-06-01
发明人： Ting-Ya Lo , Chi-Lin Teng , Hai-Ching Chen , Hsin-Yen Huang , Shau-Lin Shue , Shao-Kuan Lee , Cheng-Chin Lee
IPC分类号： H01L23/522 , H01L21/768 , H01L23/538
摘要： Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.
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公开(公告)号：US20220293462A1
公开(公告)日：2022-09-15
申请号：US17829611
申请日：2022-06-01
发明人： Shao-Kuan Lee , Hai-Ching Chen , Hsin-Yen Huang , Shau-Lin Shue , Cheng-Chin Lee
IPC分类号： H01L21/768 , H01L23/532 , H01L23/535
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
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公开(公告)号：US20220285266A1
公开(公告)日：2022-09-08
申请号：US17193595
申请日：2021-03-05
发明人： Shao-Kuan Lee , Hsin-Yen Huang , Cheng-Chin Lee , Hai-Ching Chen , Shau-Lin Shue
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768
摘要： In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.
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公开(公告)号：US20230066284A1
公开(公告)日：2023-03-02
申请号：US17412423
申请日：2021-08-26
IPC分类号： H01L23/367 , H01L23/522 , H01L23/373 , H01L21/48 , H01L23/48
摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.
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