公开(公告)号：US12033889B2

公开(公告)日：2024-07-09

申请号：US18097418

申请日：2023-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

公开(公告)号：US11990400B2

公开(公告)日：2024-05-21

申请号：US17829590

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5384 ,  H01L23/5386

Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.

公开(公告)号：US12230537B2

公开(公告)日：2025-02-18

申请号：US18230338

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Ya Lo ,  Cheng-Chin Lee ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions. The method includes forming a capping layer on exposed portions of the dielectric surface of the dielectric layer and conductive surface of the first conductive layer, forming a sacrificial layer in the one or more openings, recessing the sacrificial layer, forming a support layer on the recessed sacrificial layer in each of the one or more openings, removing the sacrificial layer to form an air gap in each of the one or more openings, forming a dielectric fill on the support layer, replacing the first conductive layer in the one or more openings with a second conductive layer, selectively forming a two-dimensional (2D) material layer on the second conductive layer, forming a first etch stop layer on the dielectric fill and the support layer, forming a second etch stop layer on the first etch stop layer and the 2D material layer, forming a dielectric material on the second etch stop layer, forming a contact opening through the dielectric material, the second etch stop layer, and the 2D material layer to expose a top surface of the second conductive layer, and forming a first conductive feature in the contact opening.

公开(公告)号：US11810815B2

公开(公告)日：2023-11-07

申请号：US17729429

申请日：2022-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/764

CPC classification number: H01L21/7682 ,  H01L23/5329 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53295

Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.

公开(公告)号：US11557511B2

公开(公告)日：2023-01-17

申请号：US17146821

申请日：2021-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

公开(公告)号：US20220359385A1

公开(公告)日：2022-11-10

申请号：US17873214

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Cheng-Chin Lee ,  Kuang-Wei Yang ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.

公开(公告)号：US10163797B2

公开(公告)日：2018-12-25

申请号：US14879259

申请日：2015-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Teng ,  Jung-Hsun Tsai ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L23/485 ,  H01L29/78

Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

公开(公告)号：US20160300760A1

公开(公告)日：2016-10-13

申请号：US15183548

申请日：2016-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76832 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.

Abstract translation: 形成保护层的方法包括确定电介质层中金属离子的预期浓度。 该方法还包括基于预期的金属离子浓度确定保护层的厚度。 该方法还包括以确定的厚度形成保护层并与电介质层接触。 保护层可以包括掺氮氮化物，碳氮化物，氮化硅或硅碳中的至少一种。

公开(公告)号：US20140167229A1

公开(公告)日：2014-06-19

申请号：US13787381

申请日：2013-03-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L23/58

CPC classification number: H01L21/76832 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer.

Abstract translation: 半导体结构包括电介质层，导电片，第一金属片，第一保护层和第二保护层。 导电片被介电层的电气材料包围。 第一金属片在介电层上方并与导电片接触。 第一保护层覆盖未被第一金属片覆盖的电介质层的电介质材料。 第二保护层在第一保护层之上。

公开(公告)号：US20250132197A1

公开(公告)日：2025-04-24

申请号：US18990711

申请日：2024-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Feng Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, an etch stop layer formed of a metal oxide composite and disposed on a top surface of the substrate, and a second conductive feature disposed on and through the etch stop layer and in contact with the first conductive feature. The metal oxide composite contains a metal element represented by M, and a top surface of the etch stop layer includes an M—O—X group, O representing oxygen, and X representing an element other than hydrogen.