公开(公告)号：US20250140605A1

公开(公告)日：2025-05-01

申请号：US18612386

申请日：2024-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ya Lo ,  Cheng-Chin Lee ,  Shao-Kuan Lee ,  Hsin-Yen Huang ,  Hsiao-Kang Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method incudes forming a metal layer over a substrate, patterning the metal layer to from first and second metal lines with a trench therebetween, depositing a sacrificial layer in a lower portion of the trench, forming a first dielectric layer on the sacrificial layer, selectively removing the sacrificial layer to form an air gap between the first and second metal lines after the forming of the first dielectric layer, and depositing a second dielectric layer over the first dielectric layer and in an upper portion of the trench.

公开(公告)号：US12272597B2

公开(公告)日：2025-04-08

申请号：US17698743

申请日：2022-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Chin Lee ,  Hsiao-Kang Chang ,  Hsin-Yen Huang ,  Cherng-Shiaw Tsai ,  Shao-Kuan Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

公开(公告)号：US12094815B2

公开(公告)日：2024-09-17

申请号：US17460824

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Chin Lee ,  Shao-Kuan Lee ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76843

Abstract: A semiconductor structure includes a substrate with a conductive structure thereon, a first dielectric layer, a conductive feature and a second dielectric layer. The substrate includes a conductive feature. The conductive feature is formed in the first dielectric layer, is electrically connected to the conductive feature. The second dielectric layer is formed on the first dielectric layer and is disposed adjacent to the conductive feature. The first dielectric layer and the second dielectric layer are made of different materials.

公开(公告)号：US12033889B2

公开(公告)日：2024-07-09

申请号：US18097418

申请日：2023-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

公开(公告)号：US11990400B2

公开(公告)日：2024-05-21

申请号：US17829590

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5384 ,  H01L23/5386

Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.

公开(公告)号：US20240145381A1

公开(公告)日：2024-05-02

申请号：US18407517

申请日：2024-01-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/53204

Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

公开(公告)号：US20220415804A1

公开(公告)日：2022-12-29

申请号：US17355613

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US20220238434A1

公开(公告)日：2022-07-28

申请号：US17718461

申请日：2022-04-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

公开(公告)号：US20150214102A1

公开(公告)日：2015-07-30

申请号：US14685217

申请日：2015-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Hsien Peng ,  Hsin-Yen Huang ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76843 ,  H01L21/02118 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer.

Abstract translation: 一种结构包括衬底，在衬底上的低k电介质层，以及延伸到低k电介质层中的导电阻挡层。 导电阻挡层包括侧壁部分。 低k电介质层中的金属线邻接导电阻挡层。 有机缓冲层位于导电阻挡层的侧壁部分和低k电介质层之间。

公开(公告)号：US20150197849A1

公开(公告)日：2015-07-16

申请号：US14153738

申请日：2014-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Huan Lee ,  Shau-Lin Shue ,  Keith Kuang-Kuo Koai ,  Hai-Ching Chen ,  Tung-Ching Tseng ,  Wen-Cheng Yang ,  Chung-En Kao ,  Ming-Han Lee ,  Hsin-Yen Huang

IPC: C23C14/58 ,  H01L21/306 ,  H01L21/768 ,  H01L21/677 ,  C23C16/455 ,  C23C16/56 ,  C23C16/44 ,  H01L21/02 ,  C23C14/24

CPC classification number: H01L21/76846 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02631 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/677 ,  H01L21/67742 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76877

Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Abstract translation: 公开了半导体器件金属化系统和方法。 在一些实施例中，用于半导体器件的金属化系统包括主机以及靠近主机设置的多个模块。 多个模块中的一个模块包括物理气相沉积（PVD）模块，并且多个模块中的一个模块包括紫外线（UV）固化模块。