公开(公告)号：US20140282326A1

公开(公告)日：2014-09-18

申请号：US13840789

申请日：2013-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01L29/6681

摘要： Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

摘要翻译： 在OD边缘上使用具有多晶硅的finFET标准单元结构的标准电池的方法。 使用finFET晶体管限定标准单元，并且在与半导体鳍片的交叉点处形成晶体管的栅极结构。 多晶硅虚拟结构形成在标准单元的有源区域或OD区域的边缘上。 在设计流程中，用于标准单元的预布局网表示意图包括对应于标准单元边缘上的多晶硅虚拟结构的三端MOS器件。 在使用标准单元形成设备布局的自动化位置和路线过程之后，提取一个布局网表。 当两个标准单元彼此邻接时，在公共边界上形成单个多晶硅虚拟结构。 然后对布局前的网表和布局后的网表进行布局与原理图比较，以验证所获得的布局。 公开了另外的方法。

公开(公告)号：US20150302136A1

公开(公告)日：2015-10-22

申请号：US14733332

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US20140282325A1

公开(公告)日：2014-09-18

申请号：US13840221

申请日：2013-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US09495506B2

公开(公告)日：2016-11-15

申请号：US14733332

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50 ,  H01L29/00 ,  H01L29/66

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US20150154339A9

公开(公告)日：2015-06-04

申请号：US13840221

申请日：2013-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US08943455B2

公开(公告)日：2015-01-27

申请号：US13840789

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01L29/6681

摘要： Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.

摘要翻译： 在OD边缘上使用具有多晶硅的finFET标准单元结构的标准电池的方法。 使用finFET晶体管限定标准单元，并且在与半导体鳍片的交叉点处形成晶体管的栅极结构。 多晶硅虚拟结构形成在标准单元的有源区域或OD区域的边缘上。 在设计流程中，用于标准单元的预布局网表示意图包括对应于标准单元边缘上的多晶硅虚拟结构的三端MOS器件。 在使用标准单元形成设备布局的自动化位置和路线过程之后，提取一个布局网表。 当两个标准单元彼此邻接时，在公共边界上形成单个多晶硅虚拟结构。 然后对布局前的网表和布局后的网表进行布局与原理图比较，以验证所获得的布局。 公开了另外的方法。

公开(公告)号：US09342647B2

公开(公告)日：2016-05-17

申请号：US14258332

申请日：2014-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F17/5045

摘要： An integrated circuit design method comprises extracting parallel-connected parameters associated with circuit components of an integrated circuit (IC) based on a determination that the circuit components are connected in parallel. The method also comprises generating a parallel netlist that describes the circuit components, the parallel netlist comprising the parallel-connected parameters. The parallel-connected parameters are taken into consideration by a simulation that determines the performance capabilities of the IC.

摘要翻译： 集成电路设计方法包括基于电路部件并联连接的确定提取与集成电路（IC）的电路部件相关联的并联连接参数。 该方法还包括生成描述电路组件的并行网表，并行网表包括并联连接的参数。 通过模拟确定并行连接的参数来确定IC的性能。

公开(公告)号：US09053283B2

公开(公告)日：2015-06-09

申请号：US13840221

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50 ,  H01L29/00

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。