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公开(公告)号：US20200287528A1
公开(公告)日：2020-09-10
申请号：US16883375
申请日：2020-05-26
IPC分类号： H03K5/1534 , H03K5/131 , H03K17/16 , H03K19/003 , H03K17/687
摘要： A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
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公开(公告)号：US20160359475A1
公开(公告)日：2016-12-08
申请号：US15244152
申请日：2016-08-23
IPC分类号： H03K5/1534 , H03K17/687
CPC分类号： H03K5/1534 , H03K5/131 , H03K17/167 , H03K17/6872 , H03K19/00315 , H03K2005/00019 , H03K2005/00058
摘要： A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.
摘要翻译： 电路包括具有第一电压电平的第一功率节点和输出节点。 耦合在第一功率和输出节点之间的驱动器晶体管分别响应于第一和第二输入信号边缘类型而导通和截止。 驱动晶体管源与第一功率节点耦合。 竞争电路包括基于输出节点信号产生反馈信号的转换速率检测电路和驱动晶体管漏极与第二电压之间的竞争晶体管。 竞争晶体管栅极基于反馈信号接收控制信号。 如果输出节点信号响应于第一输入信号边缘类型上升，则第二电压具有小于第一电压电平的电平，并且如果输出节点信号响应于第一输入信号边缘类型而降低，则大于第一电压电平。
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公开(公告)号：US20190097615A1
公开(公告)日：2019-03-28
申请号：US16206577
申请日：2018-11-30
IPC分类号： H03K5/1534 , H03K5/131 , H03K17/687 , H03K17/16 , H03K19/003 , H03K5/00
CPC分类号： H03K5/1534 , H03K5/131 , H03K17/167 , H03K17/6872 , H03K19/00315 , H03K2005/00019 , H03K2005/00058
摘要： A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
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公开(公告)号：US20160248411A1
公开(公告)日：2016-08-25
申请号：US14630934
申请日：2015-02-25
IPC分类号： H03K5/13 , H03K5/1534 , H03K17/687
CPC分类号： H03K5/1534 , H03K5/131 , H03K17/167 , H03K17/6872 , H03K19/00315 , H03K2005/00019 , H03K2005/00058
摘要： A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.
摘要翻译： 电路包括第一功率节点，输出节点，耦合在第一功率节点和输出节点之间的驱动器晶体管和竞争电路。 驱动器晶体管被配置为响应于第一类型的输入信号的边缘而被接通并且响应于第二类型的输入信号的边缘被关断。 驱动晶体管具有源极，漏极和栅极，并且驱动晶体管的源极与第一功率节点耦合。 所述竞争电路包括：控制电路，被配置为基于所述驱动晶体管的栅极处的信号产生控制信号; 以及在驱动晶体管的漏极和第二电压之间的竞争晶体管。 竞争晶体管具有被配置为接收控制信号的门。
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