公开(公告)号：US20230156995A1

公开(公告)日：2023-05-18

申请号：US18155932

申请日：2023-01-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Wei-Chang ZHAO ,  Yi-Hsin NIEN

IPC分类号： H10B10/00 ,  H01L23/522 ,  G06F30/392 ,  H01L23/528

CPC分类号： H10B10/12 ,  H01L23/5226 ,  G06F30/392 ,  H01L23/5286 ,  G03F1/70

摘要： A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region. The memory device includes buried conductive segments, each of the buried conductive segments is under a corresponding BVD structure.

公开(公告)号：US20220278111A1

公开(公告)日：2022-09-01

申请号：US17410860

申请日：2021-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hidehiro FUJIWARA ,  Yi-Hsin NIEN ,  Hung-Jen LIAO

IPC分类号： H01L27/11

摘要： An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

公开(公告)号：US20240179884A1

公开(公告)日：2024-05-30

申请号：US18430661

申请日：2024-02-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hidehiro FUJIWARA ,  Yi-Hsin NIEN ,  Hung-Jen LIAO

IPC分类号： H10B10/00

CPC分类号： H10B10/18 ,  H10B10/12

摘要： An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

公开(公告)号：US20230238056A1

公开(公告)日：2023-07-27

申请号：US17585824

申请日：2022-01-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Hsin NIEN ,  Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Yen-Huei CHEN

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/419

CPC分类号： G11C11/412 ,  H01L27/1104 ,  G11C11/419

摘要： A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

公开(公告)号：US20210408011A1

公开(公告)日：2021-12-30

申请号：US17225627

申请日：2021-04-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Wei-Chang ZHAO ,  Yi-Hsin NIEN

IPC分类号： H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  G06F30/392

摘要： A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage.