公开(公告)号：US12254262B2

公开(公告)日：2025-03-18

申请号：US17462747

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Chung Chen ,  Shufang Fu ,  Kuan-Hung Liu ,  Chiao-Chun Hsu ,  Fu-Yu Shih ,  Chi-Feng Huang ,  Chu Fu Chen

IPC: G06F30/398 ,  H01L29/66 ,  G06F119/02 ,  G06F119/18

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.