公开(公告)号：US20240087966A1

公开(公告)日：2024-03-14

申请号：US18171286

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chu Fu Chen ,  Chun Hao Liao

IPC: H01L21/66 ,  H10B10/00 ,  H10K59/12 ,  H10K59/127 ,  H10K59/131

CPC classification number: H01L22/30 ,  H01L22/12 ,  H01L22/14 ,  H10B10/12 ,  H10K59/1201 ,  H10K59/127 ,  H10K59/131

Abstract: A driver structure for an organic light-emitting diode (OLED) device is provided. The driver structure includes a front-end-of-line (FEOL) layer; a back-end-of-line (BEOL) layer disposed on the FEOL layer; and a customer BEOL layer disposed on the BEOL layer. The BEOL layer includes a customer BEOL electrical checking structure. The customer BEOL electrical checking structure has a plurality of memory cells that include a first memory cell vertically aligned with and corresponds to two adjacent pixel regions. The customer BEOL layer includes six bottom structures corresponding to the two adjacent pixel regions and connected in series to form a first electrical path and a second electrical path each electrically connected to the first memory cell. The first memory cell is configured to detect an anomaly of electrical resistance of the first and second electrical path.

公开(公告)号：US09658278B2

公开(公告)日：2017-05-23

申请号：US14163062

申请日：2014-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Po-Ju Chiu ,  Jun Yean Chiou ,  Chao-Jen Cheng

IPC: H01L51/56 ,  H01L21/70 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2648 ,  G01R31/2831 ,  H01L22/12 ,  H01L22/34

Abstract: A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.

公开(公告)号：US12020993B2

公开(公告)日：2024-06-25

申请号：US17199119

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Yu Chuan Liang ,  Chu Fu Chen

IPC: H01L21/66 ,  H01L21/266 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/085

CPC classification number: H01L22/14 ,  H01L21/266 ,  H01L22/32 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/06515

Abstract: A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.

公开(公告)号：US11024552B2

公开(公告)日：2021-06-01

申请号：US16739941

申请日：2020-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Mingo Liu ,  Chiou Jun Yean

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L25/16 ,  H01L25/075 ,  G01R31/26 ,  H01L33/00

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

公开(公告)号：US11842920B2

公开(公告)日：2023-12-12

申请号：US17353618

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66477

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

公开(公告)号：US11075107B2

公开(公告)日：2021-07-27

申请号：US16371900

申请日：2019-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Chun-Wei Hsu ,  Chia-Cheng Pao

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

公开(公告)号：US12254262B2

公开(公告)日：2025-03-18

申请号：US17462747

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Chung Chen ,  Shufang Fu ,  Kuan-Hung Liu ,  Chiao-Chun Hsu ,  Fu-Yu Shih ,  Chi-Feng Huang ,  Chu Fu Chen

IPC: G06F30/398 ,  H01L29/66 ,  G06F119/02 ,  G06F119/18

Abstract: A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

公开(公告)号：US11936299B2

公开(公告)日：2024-03-19

申请号：US17027032

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chu Fu Chen ,  Chi-Feng Huang ,  Chia-Chung Chen ,  Chin-Lung Chen ,  Victor Chiang Liang ,  Chia-Cheng Pao

IPC: H02M3/158 ,  H01L21/84 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/80 ,  H01L21/265

CPC classification number: H02M3/1582 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/80 ,  H01L21/26586 ,  H02M3/158

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

公开(公告)号：US10535572B2

公开(公告)日：2020-01-14

申请号：US15193542

申请日：2016-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hao Liao ,  Chu Fu Chen ,  Mingo Liu ,  Chiou Jun Yean

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L25/16

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

公开(公告)号：US20250022932A1

公开(公告)日：2025-01-16

申请号：US18351761

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chiao-Chun Hsu ,  Chu Fu Chen ,  Ting-Yu Chen

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Some embodiments relate to an integrated device, including a semiconductor film accommodating a two-dimensional carrier gas (2DCG) over a substrate; a first source/drain electrode over the semiconductor film; a second source/drain electrode over the semiconductor film; a semiconductor capping structure between the first source/drain electrode and the second source/drain electrode; a first gate overlying the semiconductor capping structure and between the first source/drain electrode and the second source/drain electrode in a first direction; a first helping gate overlying the semiconductor capping structure and bordering the first gate, wherein the first helping gate and the second source/drain electrode are arranged in a line extending in a second direction transverse to the first direction.