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142 条记录 (耗时 0.029 秒)

    Integrated circuit layout method, device, and system
    6.
    发明授权
    Integrated circuit layout method, device, and system 有权

    公开(公告)号：US11355488B2

    公开(公告)日：2022-06-07

    申请号：US16936175

    申请日：2020-07-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Ying Chen ,  Lee-Chung Lu ,  Li-Chun Tien ,  Ta-Pen Guo

    IPC分类号： H01L27/092 ,  H01L27/02 ,  G06F30/392

    摘要： A method of generating a layout diagram of an IC cell includes defining a boundary recess in a boundary of the cell by extending a first portion of the boundary along a first gate track, extending a second portion of the boundary from the first gate track to a second gate track, the second portion being contiguous with the first portion, and extending a third portion of the boundary from the first gate track to the second gate track, the third portion being contiguous with the first portion. An active region is positioned in the cell by extending the active region across a third gate track, wherein the first gate track is between the second gate track and the third gate track. The layout diagram is stored on a non-transitory computer-readable medium.

    Semiconductor device including deep vias, and method of generating layout diagram for same
    7.
    发明授权
    Semiconductor device including deep vias, and method of generating layout diagram for same 有权

    公开(公告)号：US11127673B2

    公开(公告)日：2021-09-21

    申请号：US16530808

    申请日：2019-08-02

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Ta-Pen Guo ,  Li-Chun Tien ,  Chien-Ying Chen ,  Lee-Chung Lu

    IPC分类号： H01L23/522 ,  G06F30/394

    摘要： A method (of generating a layout diagram) includes: generating one or more first conductive patterns representing corresponding conductive material in the first metallization layer, long axes of the first conductive patterns extending substantially in a first direction; generating a first deep via pattern representing corresponding conductive material in each of the second via layer, the first metallization layer, and the first via layer; relative to the first direction and a second direction substantially perpendicular to the first direction, aligning the first deep via pattern to overlap a corresponding component pattern representing conductive material included in an electrical path of a terminal of a corresponding transistor in the transistor layer; and configuring a size of the first deep via pattern in the first direction to be substantially less than a permissible minimum length of a conductive pattern in the first metallization layer.

    Semiconductor device having engineering change order (ECO) cells
    10.
    发明授权
    Semiconductor device having engineering change order (ECO) cells 有权

    公开(公告)号：US10565345B2

    公开(公告)日：2020-02-18

    申请号：US16206881

    申请日：2018-11-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Li-Chun Tien ,  Ting-Wei Chiang ,  Shun Li Chen ,  Ting Yu Chen ,  XinYong Wang

    IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L27/02 ,  H01L27/118 ,  H01L23/522 ,  H01L23/528

    摘要： A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps.