公开(公告)号：US20210134371A1

公开(公告)日：2021-05-06

申请号：US17120702

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Michael Clinton ,  Bryan David Sheffield ,  Marty Tsai ,  Rajinder Singh

IPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/08 ,  G11C7/18 ,  G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C11/419

摘要： A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines

公开(公告)号：US09959916B2

公开(公告)日：2018-05-01

申请号：US15589313

申请日：2017-05-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Michael Clinton

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  G11C8/10 ,  G11C8/06 ,  G11C8/08 ,  G11C11/418 ,  G11C11/417

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/065 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C11/417 ,  G11C11/418

摘要： A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

公开(公告)号：US20190295656A1

公开(公告)日：2019-09-26

申请号：US16240175

申请日：2019-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Michael Clinton ,  Bryan David Sheffield ,  Marty Tsai ,  Rajinder Singh

IPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/08 ,  G11C7/12 ,  G11C7/10 ,  G11C7/18

摘要： A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines

公开(公告)号：US09666253B2

公开(公告)日：2017-05-30

申请号：US14924069

申请日：2015-10-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Michael Clinton

IPC分类号： G11C7/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  G11C8/10 ,  G11C8/06 ,  G11C8/08

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/065 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C11/417 ,  G11C11/418

摘要： A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.