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公开(公告)号：US20250072070A1
公开(公告)日：2025-02-27
申请号：US18507039
申请日：2023-11-11
Inventor： Chen An Hsu , Chien-Wei Lee , Anhao Cheng , Yen-Liang Lin , Ru-Shang Hsiao , Wei-Lun Chung
IPC: H01L29/08 , H01L21/8234 , H01L27/088 , H01L29/66
Abstract: A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.
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公开(公告)号：US20240395947A1
公开(公告)日：2024-11-28
申请号：US18790105
申请日：2024-07-31
Inventor： Sung-Hsin Yang , Jung-Chi Jeng , Ru-Shang Hsiao
Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit containing a transistor, a sidewall spacer, a semiconductor region with multiple doped layers, an insulator layer, and a metal layer. The transistor having a channel region, an insulating layer surrounding three sides of the channel region, and a conductive layer surrounding three sides of the channel region. The semiconductor region has an outer sidewall facing a side of the sidewall spacer opposite from the transistor. The insulator layer surrounds three sides of the semiconductor region. The metal layer surrounds three sides of the insulator layer. The semiconductor region has a width equal to a width of the channel region the transistor along a first line, and the semiconductor region has a second width less than a second width of the channel region of the transistor along a second line.
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公开(公告)号：US20230067587A1
公开(公告)日：2023-03-02
申请号：US17460200
申请日：2021-08-28
Inventor： Sung-Hsin Yang , Jung-Chi Jeng , Ru-Shang Hsiao
IPC: H01L27/06 , H01L27/092 , H01L29/66 , H01L29/423 , H01L29/40 , H01L21/8238
Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first three-dimensional semiconductor structure of a first conductivity type protruding from a surface of the semiconductor substrate. The semiconductor device includes a second three-dimensional semiconductor structure of a second conductivity type protruding from the surface of the semiconductor substrate. The semiconductor device includes a first transistor having a first source/drain structure formed in the first three-dimensional semiconductor structure, a second source/drain structure formed in the second three-dimensional semiconductor structure, a first gate structure straddling a first portion of the first three-dimensional semiconductor structure and a first portion of the second three-dimensional semiconductor structure, and a second gate structure straddling a second portion of the second three-dimensional semiconductor structure.
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公开(公告)号：US11271102B2
公开(公告)日：2022-03-08
申请号：US16717528
申请日：2019-12-17
Inventor： Ru-Shang Hsiao , Chi-Cherng Jeng , Chih-Mu Huang
IPC: H01L29/735 , H01L23/29 , H01L23/31 , H01L29/66 , H01L29/78
Abstract: A semiconductor structure includes a substrate, a gate region, a source/drain region, a composite layer, an ILD layer, a first plug and a second plug. The composite layer includes a first sublayer and a third layer including a first material, and a second sublayer including a second material. The second sublayer is between the first sublayer and the third sublayer. The first plug is through the ILD layer and electrically connected to the gate region. The second plug is through the ILD layer and the composite layer and electrically connected to the source/drain region. The second plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer. Widths of the first portion and the third portion are smaller than a width of the second portion. The second portion has a substantially curved sidewall profile.
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公开(公告)号：US10651041B2
公开(公告)日：2020-05-12
申请号：US16429595
申请日：2019-06-03
Inventor： Ru-Shang Hsiao , Chi-Cherng Jeng , Chih-Mu Huang
IPC: H01L21/28 , H01L29/423 , H01L29/66
Abstract: A semiconductor structure and a method of forming the same are provided. According to an aspect of the disclosure, a semiconductor structure includes a first layer having a bottom portion and a sidewall connected to the bottom portion, a metal layer disposed above the bottom portion of the first layer, and a second layer disposed above the metal layer and laterally surrounded by the sidewall of the first layer. The metal layer includes a periphery and a middle portion surrounded by the periphery, the middle portion being thicker than the periphery, and a first etch rate of an etchant with respect to the metal layer is uniform throughout the metal layer and is greater than a second etch rate of the etchant with respect to the second layer.
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Patent Agency Ranking
公开(公告)号：US20160155806A1
公开(公告)日：2016-06-02
申请号：US15004365
申请日：2016-01-22
Inventor： Chen-Chieh Chiang , Chih-Kang Chao , Chih-Mu Huang , Ling-Sung Wang , Ru-Shang Hsiao
CPC classification number: H01L29/1054 , H01L29/4966 , H01L29/517 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66636 , H01L29/66651 , H01L29/78 , H01L29/7833 , H01L29/7834
Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.
Abstract translation: 公开了半导体器件及其形成方法。 半导体器件包括衬底，以及形成在衬底中的源区和漏区。 半导体器件还包括形成在源极区域和漏极区域之间的衬底的凹部中的杂质扩散停止层，其中杂质扩散停止层覆盖凹部的底部和侧壁。 半导体器件还包括形成在杂质扩散停止层上和凹槽中的沟道层，以及形成在沟道层上的栅叠层。
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公开(公告)号：US20250056819A1
公开(公告)日：2025-02-13
申请号：US18402035
申请日：2024-01-02
Inventor： Wei-Lun Chung , Chung-Lei Chen , Anhao Cheng , Chien-Wei Lee , Yen-Liang Lin , Ru-Shang Hsiao
Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.
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公开(公告)号：US20240429260A1
公开(公告)日：2024-12-26
申请号：US18212487
申请日：2023-06-21
Inventor： Chuan-Cheng Tsou , Sung-Hsin Yang , Jung-Chi Jeng , Chen-Chieh Chiang , Ru-Shang Hsiao , Ling-Sung Wang
IPC: H01L27/146 , H01L25/065
Abstract: Embodiments of the present disclosure relate to methods for forming a film stack during fabrication or bonding process. The film stack according to present disclosure may reduce wet dip attacking to semiconductor substrate during bonding, such as bonding between an image sensor substrate and a logic device substrate. The film stack according to the present disclosure may be used to modulate stress and wafer warpage to improve bonding adhesion and device performance during various packaging schemes, such as CoWoS, SoIC, or the like. The film stack according to the present disclosure may be used to improve bonding process and device performance in both wafer-to-wafer bonding and die-to-die bonding.
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公开(公告)号：US10510877B2
公开(公告)日：2019-12-17
申请号：US15986619
申请日：2018-05-22
Inventor： Ru-Shang Hsiao , Chi-Cherng Jeng , Chih-Mu Huang
IPC: H01L29/78 , H01L29/735 , H01L23/29 , H01L23/31
Abstract: A semiconductor structure includes a substrate, a source/drain region, a composite layer and a plug. The source/drain region and the composite layer are over the substrate. The composite layer includes a first sublayer having a first material, a second sublayer having a second material, and a third sublayer having the first material. A bandgap of the second material is larger than that of the first material. The second sublayer is between the first sublayer and the third sublayer. The plug is through the composite layer, and electrically connected to the source/drain region. The plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, and a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion.
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公开(公告)号：US10312092B2
公开(公告)日：2019-06-04
申请号：US15875244
申请日：2018-01-19
Inventor： Ru-Shang Hsiao , Chi-Cherng Jeng , Chih-Mu Huang
IPC: H01L21/28 , H01L29/423 , H01L29/66
Abstract: A semiconductor structure includes a first layer having a recessed surface, a metal layer disposed above the first layer, and a second layer disposed above the metal layer and confined by the recessed surface. The second layer includes a first lateral side and a second lateral side. A first thickness of the second layer in a middle portion between the first lateral side and the second lateral side is less than a second thickness of at least one of the first lateral side and the second lateral side of the second layer. The metal layer has a same material across an entire range covered by the second layer.
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