公开(公告)号：US20220328455A1

公开(公告)日：2022-10-13

申请号：US17538029

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Hiroki Noguchi ,  Hidehiro Fujiwara ,  Yih Wang

IPC: H01L25/065 ,  H01L25/00

Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).

公开(公告)号：US12068284B2

公开(公告)日：2024-08-20

申请号：US17537026

申请日：2021-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Hiroki Noguchi ,  Mahmut Sinangil ,  Yih Wang

IPC: H01L25/18 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L21/76898 ,  H01L2225/06544

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.

公开(公告)号：US20220302088A1

公开(公告)日：2022-09-22

申请号：US17537026

申请日：2021-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Hiroki Noguchi ,  Mahmut Sinangil ,  Yih Wang

IPC: H01L25/065 ,  H01L25/18

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.

公开(公告)号：US11903188B2

公开(公告)日：2024-02-13

申请号：US17673126

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US20240371434A1

公开(公告)日：2024-11-07

申请号：US18773354

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Chia-En Huang ,  Yih Wang ,  Jonathan Tsung-Yung Chang

IPC: G11C11/4097 ,  G11C11/4091

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

公开(公告)号：US20240363594A1

公开(公告)日：2024-10-31

申请号：US18768421

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Hiroki Noguchi ,  Mahmut Sinangil ,  Yih Wang

IPC: H01L25/065 ,  H01L21/768 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L21/76898 ,  H01L2225/06544

Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.

公开(公告)号：US20240243105A1

公开(公告)日：2024-07-18

申请号：US18620591

申请日：2024-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Hiroki Noguchi ,  Hidehiro Fujiwara ,  Yih Wang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).

公开(公告)号：US12087354B2

公开(公告)日：2024-09-10

申请号：US17684951

申请日：2022-03-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Chia-En Huang ,  Yih Wang ,  Jonathan Tsung-Yung Chang

IPC: G11C11/4097 ,  G11C11/4091

CPC classification number: G11C11/4097 ,  G11C11/4091

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

公开(公告)号：US11978723B2

公开(公告)日：2024-05-07

申请号：US17538029

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Hiroki Noguchi ,  Hidehiro Fujiwara ,  Yih Wang

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).

公开(公告)号：US20230134975A1

公开(公告)日：2023-05-04

申请号：US17684951

申请日：2022-03-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsien Yang ,  Chia-En Huang ,  Yih Wang ,  Jonathan Tsung-Yung Chang

IPC: G11C11/4097 ,  G11C11/4091

Abstract: A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.