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公开(公告)号：US20240386979A1
公开(公告)日：2024-11-21
申请号：US18786718
申请日：2024-07-29
Inventor： Meng-Sheng Chang , Yoshitaka Yamauchi , Perng-Fei Yuh
Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.
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公开(公告)号：US11953927B2
公开(公告)日：2024-04-09
申请号：US17238064
申请日：2021-04-22
Inventor： Perng-Fei Yuh , Yoshitaka Yamauchi , Yih Wang
Abstract: The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.
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公开(公告)号：US11664081B2
公开(公告)日：2023-05-30
申请号：US17557268
申请日：2021-12-21
Inventor： Meng-Sheng Chang , Yoshitaka Yamauchi , Perng-Fei Yuh
Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.
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公开(公告)号：US12087378B2
公开(公告)日：2024-09-10
申请号：US18318000
申请日：2023-05-16
Inventor： Meng-Sheng Chang , Yoshitaka Yamauchi , Perng-Fei Yuh
Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.
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公开(公告)号：US11763875B2
公开(公告)日：2023-09-19
申请号：US17331340
申请日：2021-05-26
Inventor： Yoshitaka Yamauchi , Meng-Sheng Chang , Hiroki Noguchi , Perng-Fei Yuh
IPC: G11C8/10 , G11C11/408 , G11C11/4096 , G11C11/4094
CPC classification number: G11C11/4087 , G11C11/4085 , G11C11/4094 , G11C11/4096
Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.
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Patent Agency Ranking
公开(公告)号：US20220383934A1
公开(公告)日：2022-12-01
申请号：US17331340
申请日：2021-05-26
Inventor： Yoshitaka Yamauchi , Meng-Sheng Chang , Hiroki Noguchi , Perng-Fei Yuh
IPC: G11C11/408 , G11C11/4094 , G11C11/4096
Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.
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公开(公告)号：US20220336031A1
公开(公告)日：2022-10-20
申请号：US17557268
申请日：2021-12-21
Inventor： Meng-Sheng Chang , Yoshitaka Yamauchi , Perng-Fei Yuh
Abstract: Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.
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公开(公告)号：US12210368B2
公开(公告)日：2025-01-28
申请号：US18599233
申请日：2024-03-08
Inventor： Perng-Fei Yuh , Yoshitaka Yamauchi , Yih Wang
Abstract: The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.
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公开(公告)号：US11903188B2
公开(公告)日：2024-02-13
申请号：US17673126
申请日：2022-02-16
Inventor： Perng-Fei Yuh , Yih Wang , Meng-Sheng Chang , Jui-Che Tsai , Ku-Feng Lin , Yu-Wei Lin , Keh-Jeng Chang , Chansyun David Yang , Shao-Ting Wu , Shao-Yu Chou , Philex Ming-Yan Fan , Yoshitaka Yamauchi , Tzu-Hsien Yang
Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
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公开(公告)号：US20230377629A1
公开(公告)日：2023-11-23
申请号：US18361559
申请日：2023-07-28
Inventor： Yoshitaka Yamauchi , Meng-Sheng Chang , Hiroki Noguchi , Perng-Fei Yuh
IPC: G11C11/408 , G11C11/4096 , G11C11/4094
CPC classification number: G11C11/4087 , G11C11/4096 , G11C11/4094 , G11C11/4085
Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.
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