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公开(公告)号:US11768989B2
公开(公告)日:2023-09-26
申请号:US17558157
申请日:2021-12-21
Inventor: Chi-Yu Lu , Hui-Zhong Zhuang , Pin-Dai Sue , Yi-Hsin Ko , Li-Chun Tien
IPC: G06F30/392 , G06F30/398
CPC classification number: G06F30/392 , G06F30/398
Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.
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公开(公告)号:US11216608B2
公开(公告)日:2022-01-04
申请号:US16664242
申请日:2019-10-25
Inventor: Chi-Yu Lu , Hui-Zhong Zhuang , Li-Chun Tien , Pin-Dai Sue , Yi-Hsin Ko
IPC: G06F30/392 , G06F30/398
Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.
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公开(公告)号:US12299373B2
公开(公告)日:2025-05-13
申请号:US18447187
申请日:2023-08-09
Inventor: Chi-Yu Lu , Hui-Zhong Zhuang , Pin-Dai Sue , Yi-Hsin Ko , Li-Chun Tien
IPC: G06F30/392 , G06F30/398
Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.
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