Reduced area standard cell abutment configurations

    公开(公告)号:US12299373B2

    公开(公告)日:2025-05-13

    申请号:US18447187

    申请日:2023-08-09

    Abstract: A method of designing a semiconductor device including the operations of analyzing a vertical abutment between a first standard cell block and a second cell block and, if a mismatch is identified between the first standard cell block and the second cell block initiating the selection of a first modified cell block that reduces the mismatch and a spacing between the first modified cell block and the second cell block, the first modified cell block comprising a first abutment region having a continuous active region arranged along a first axis parallel to an edge of the vertical abutment, and replacing the first standard cell block with the first modified cell block to obtain a first modified layout design and devices manufactured according to the method.

    Isolation circuit between power domains

    公开(公告)号:US11526647B2

    公开(公告)日:2022-12-13

    申请号:US17115436

    申请日:2020-12-08

    Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

    TIE OFF DEVICE
    3.
    发明申请

    公开(公告)号:US20220352166A1

    公开(公告)日:2022-11-03

    申请号:US17863175

    申请日:2022-07-12

    Abstract: An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

    Adaptive Fin Design for FinFETs
    10.
    发明申请
    Adaptive Fin Design for FinFETs 审中-公开
    FinFET的自适应鳍设计

    公开(公告)号:US20140203378A1

    公开(公告)日:2014-07-24

    申请号:US14220930

    申请日:2014-03-20

    Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

    Abstract translation: 设计标准单元的方法包括确定标准单元中的半导体鳍片的最小鳍间距,其中半导体鳍片是FinFET的部分; 以及确定所述标准单元上的底部金属层中的金属线的最小金属间距,其中所述最小金属间距大于所述最小鳍间距。 将标准单元放置在集成电路中并在半导体晶片上实现。

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